Firestorm: STP (Q) measurements

Code:

  stp q0, q1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
9005	1165	8	0	2	1	0	1150	0	15	25	2000	2000	2000	10184	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	31	2001	0	1	2001	1	31	511	1	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	2	1	0	1150	15	15	25	2000	2000	2000	10000	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	31	2001	0	0	2000	1	0	511	0	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	5	1	0	1150	0	0	25	2000	2000	2000	10000	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	0	2000	0	0	2001	1	0	511	0	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	0	0	0	1150	15	0	25	2000	2000	2000	10000	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	31	2000	0	4	2001	0	31	511	0	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	5	0	0	1150	15	0	25	2000	2000	2000	10057	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	31	2001	0	0	2000	1	31	511	0	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	0	0	0	1150	15	15	25	2000	2000	2000	10013	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	0	2000	0	0	2000	1	0	512	0	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	0	1	0	1150	15	15	25	2000	2000	2000	10000	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	0	2001	0	0	2001	1	31	512	0	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	5	1	0	1150	15	15	25	2000	2000	2000	10057	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	31	2000	0	1	2001	1	31	512	0	16	0	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	0	0	0	1150	0	15	25	2000	2000	2000	10112	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	0	2001	0	0	2001	0	31	512	0	16	0	0	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	2	1	0	1150	0	15	25	2000	2000	2000	10057	1140	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	31	2001	0	0	2000	1	31	511	0	16	0	0	1162	2000	1166	1166	1166	1166	1166

Count: 8

Code:

  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	79	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80042	600	0	0	0	0	6	3	1	0	0	80027	16	16	0	25	160100	100	160000	100	160216	500	3684236	1	0	80015	0	80049	80042	59953	3	60008	160100	0	200	160000	200	320000	80040	80183	2	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160000	0	5	160002	2	0	0	0	0	0	5110	0	16	1	1	80039	0	160000	100	80043	80041	80041	80043	80043
160204	80042	599	0	0	0	0	0	3	0	0	0	80036	16	0	0	25	160100	100	160000	100	160000	500	3679832	0	0	80017	0	80042	80042	59955	3	59998	160100	0	200	160000	200	320000	80042	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	5	160002	2	34	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80041	80041	80052	80043	80043
160204	80042	599	0	0	0	0	0	3	0	0	0	80027	0	16	0	25	160100	100	160000	100	160000	500	3679424	0	0	80017	0	80050	80042	59953	3	60000	160100	0	200	160000	200	320000	80049	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	0	2	160002	0	34	0	0	0	0	5110	1	16	1	1	80037	0	160000	100	80043	80043	80043	80043	80043
160204	80042	599	0	0	0	0	0	9	0	0	0	80035	16	16	0	25	160100	100	160000	100	160000	500	3679856	0	0	80026	0	80042	80040	59964	3	60000	160100	0	200	160120	200	320240	80049	80318	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	160002	2	34	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80041	80041	80043	80051	80052
160204	80051	600	0	0	0	0	0	3	0	0	0	80025	0	16	0	25	160100	100	160000	100	160000	500	3679424	0	0	80017	0	80049	80042	59963	3	60000	160100	0	200	160000	200	320000	80051	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160000	0	2	160002	2	34	0	0	0	0	5110	1	16	1	1	80118	0	160000	100	80041	80050	80051	80043	80041
160204	80042	626	0	0	0	0	0	3	1	0	0	80027	16	16	0	25	160100	100	160000	100	160000	500	3679424	0	0	80017	0	80051	80042	59953	3	60232	160100	0	200	160000	200	320000	80051	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	0	160002	0	0	160002	2	34	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80043	80043	80043	80051	80051
160204	80049	600	0	0	0	0	0	3	1	0	0	80027	0	0	0	25	160100	100	160000	100	160000	500	3679352	0	0	80015	0	80042	80040	59964	3	59998	160100	0	200	160000	200	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	2	160000	0	34	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80043	80043	80043	80052	80052
160204	80051	599	0	0	0	0	6	6	1	0	0	80025	16	16	2	25	160100	100	160000	100	160000	500	3679424	0	0	80015	0	80042	80040	59953	3	60000	160100	0	200	160000	200	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	2	160002	0	34	0	0	0	0	5110	1	16	1	1	80048	0	160000	100	80043	80041	80043	80043	80041
160204	80042	600	0	0	0	0	0	3	0	0	0	80025	0	0	1938	1105	161426	102	160000	100	160000	500	3679424	0	0	80017	0	80042	80042	59955	3	60000	160100	0	200	160000	200	320000	80042	80049	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	0	160000	2	34	0	0	0	0	5110	1	16	1	1	80039	0	160000	100	80043	80043	80043	80051	80052
160204	80130	599	0	0	0	0	0	3	1	0	0	80025	16	16	0	25	160100	100	160000	100	160000	500	3679424	0	0	80017	0	80051	80042	59953	3	60000	160100	0	200	160000	200	320000	80050	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	34	0	0	160002	0	8	160062	2	34	0	0	0	0	5110	1	16	1	1	80037	0	160000	100	80041	80323	82328	80745	81295

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80042	599	0	0	0	0	0	0	0	3	1	0	0	80025	16	16	1	25	160010	10	160000	10	160000	50	3679352	1	0	80016	80042	80043	59978	3	60022	160010	20	160000	20	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	4	42	0	0	5020	1	16	0	1	1	80040	160000	10	80044	80041	80044	80044	80041
160024	80043	600	0	0	0	0	0	0	0	3	0	0	0	80028	0	0	0	25	160010	10	160000	10	160000	50	3679352	1	0	80021	80043	80040	59975	3	60023	160010	20	160000	20	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	44	0	0	160002	0	0	6	160000	2	42	0	0	5020	1	16	0	1	1	80040	160000	10	80044	80044	80041	80044	80044
160024	80042	600	0	0	0	0	0	0	0	3	1	0	0	80027	16	16	0	55	160010	10	160000	10	160000	50	3679352	1	0	80018	80043	80042	59977	3	60023	160010	20	160000	20	320000	80043	80040	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	0	0	0	160002	2	42	0	0	5020	1	16	0	1	1	80039	160000	10	80044	80044	80044	80041	80043
160024	80040	599	0	0	0	0	0	0	0	0	0	0	0	80027	16	0	0	25	160010	10	160000	10	160000	50	3679448	1	0	80015	80040	80040	59977	3	60020	160010	20	160000	20	320000	80043	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160000	0	0	2	160002	2	42	0	0	5020	1	16	0	1	1	80039	160000	10	80043	80043	80043	80043	80041
160024	80040	600	0	0	0	0	0	0	0	3	1	0	0	80027	0	16	0	25	160010	10	160000	10	160000	50	3679448	1	0	80021	80042	80042	59977	3	60023	160010	20	160000	20	320000	80040	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	1	0	0	160002	2	42	0	0	5020	1	16	0	1	1	80039	160000	10	80041	80043	80043	80043	80043
160024	80042	600	0	0	0	0	0	0	0	3	0	0	0	80027	0	0	0	25	160010	10	160000	10	160000	50	3679352	1	0	80019	80043	80043	59978	3	60022	160010	20	160000	20	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	2	160002	2	42	0	0	5020	1	16	0	1	1	80040	160000	10	80044	80044	80044	80044	80044
160024	80042	600	0	0	0	0	0	0	6	3	1	0	0	80027	16	16	0	25	160010	10	160000	10	160000	50	3679448	1	0	80017	80042	80042	59975	3	60022	160010	20	160000	20	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	42	0	0	160002	0	0	5	160002	2	0	0	0	5020	1	16	0	1	1	80039	160000	10	80044	80044	80041	80044	80041
160024	80043	600	0	0	0	0	0	0	0	3	0	0	0	80027	0	16	0	25	160010	10	160000	10	160000	50	3679448	1	0	80019	80042	80043	59975	3	60020	160010	20	160000	20	320000	80042	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	0	160000	2	42	0	0	5020	1	16	0	1	1	80039	160000	10	80041	80043	80043	80041	80041
160024	80040	599	0	0	0	0	0	0	66	3	0	0	0	80027	16	16	0	25	160010	10	160000	10	160000	50	3679448	1	0	80019	80042	80043	59978	3	60022	160010	20	160000	20	320000	80040	80043	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160000	43	0	2	160002	2	0	0	0	5020	1	16	0	1	1	80039	160000	10	80041	80043	80041	80043	80043
160024	80043	599	0	0	0	0	0	0	0	0	1	0	0	80025	16	16	1	25	160010	10	160060	10	160000	50	3679448	1	0	80027	80040	80042	59977	3	60020	160010	20	160000	20	320000	80042	80040	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	2	160002	2	42	0	0	5020	1	16	0	1	1	80037	160000	10	80324	80602	80180	80461	80885

STP (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations