Firestorm: STP (S) measurements

Code:

  stp s0, s1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	9	0	0	1	1151	0	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	0	514	5	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	1	1	1151	8	0	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	0	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	0	1151	8	0	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	6	1	1	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	25	1000	0	0	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	3	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	6	1	1	1151	8	0	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	6	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	0	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	4	1	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	0	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	1000	0	0	1000	0	15	514	4	16	4	4	1163	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stp s0, s1, [x6]
  stp s0, s1, [x6]
  stp s0, s1, [x6]
  stp s0, s1, [x6]
  stp s0, s1, [x6]
  stp s0, s1, [x6]
  stp s0, s1, [x6]
  stp s0, s1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	22	23	24	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	40043	300	0	0	3	0	0	0	2318	40027	0	16	0	25	162426	100	82353	80000	100	80000	80000	500	1839832	649539	1	40021	40043	40049	19962	0	3	20007	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	5	80002	0	34	0	0	5110	0	1	16	1	1	40039	0	80000	80000	100	40044	40043	40043	40044	40043
160204	40048	300	0	0	3	1	0	0	3255	40028	16	16	0	25	163033	100	82928	80000	100	80000	80000	500	1839712	645664	1	40021	40049	40043	19959	0	3	20001	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	2	80002	0	34	0	0	5110	0	1	16	1	1	40040	0	80000	80000	100	40043	40043	40044	40049	40049
160204	40042	300	0	0	6	0	0	0	2282	40027	0	16	0	25	162426	100	82326	80000	100	80000	80000	500	1839712	645664	1	40024	40043	40043	19959	0	3	20000	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	8	80002	2	0	0	0	5110	0	1	16	1	1	40039	0	80000	80000	100	40043	40050	40044	40049	40044
160204	40049	300	0	0	0	0	0	0	1486	40028	16	16	0	25	161983	100	82782	80000	100	80000	80000	500	1839712	648797	0	40021	40042	40042	19962	0	3	20001	160100	200	80000	80000	200	160000	160000	40043	40049	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	2	80002	0	0	0	0	5110	0	1	16	1	1	40039	1	80000	80000	100	40043	40050	40043	40050	40043
160204	40042	300	1	0	3	1	0	0	2361	40034	0	0	0	25	163028	100	82928	80000	100	80000	80000	500	1839712	645664	1	40021	40043	40043	20259	2	3	20006	160100	200	80000	80000	200	160000	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	2	80002	0	34	0	0	5110	0	1	16	1	1	40039	0	80000	80000	100	40043	40043	40044	40043	40043
160204	40042	300	0	0	3	0	0	0	3909	40028	16	16	0	25	161585	100	82253	80000	100	80000	80000	500	1839712	646049	0	40023	40042	40042	19959	0	3	20007	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	2	80002	2	0	0	0	5110	0	1	16	1	1	40045	0	80000	80000	100	40044	40044	40043	40043	40043
160204	40042	300	0	0	3	1	0	0	2326	40027	16	16	0	25	162422	100	82353	80000	100	80000	80000	500	1839712	648813	1	40021	40042	40042	19959	0	3	20006	160100	200	80000	80000	200	160000	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	3	80000	2	34	0	0	5110	0	1	16	1	1	40046	0	80000	80000	100	40044	40043	40050	40043	40043
160204	40043	300	0	0	3	1	0	0	2326	40033	16	16	0	25	163038	100	83264	80000	100	80000	80216	500	1847884	652370	0	40021	40043	40049	19962	0	3	20000	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	0	80000	2	0	0	0	5110	0	1	16	1	1	40039	0	80000	80000	100	40043	40050	40043	40049	40043
160204	40049	302	0	0	3	1	0	0	2928	40028	16	16	0	25	162426	100	82253	80000	100	80000	80000	500	1839808	644469	1	40021	40049	40048	19962	0	3	20001	160100	200	80000	80000	200	160000	160000	40042	40048	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	12	2	80000	0	34	0	0	5110	0	1	16	1	1	40040	0	80000	80000	100	40044	40043	40043	40044	40043
160204	40042	300	0	0	3	0	0	0	2322	40028	16	16	0	51	163791	100	83746	80000	100	80116	80000	500	1839712	646987	1	40021	40049	40043	19959	0	3	20001	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	2	80002	2	34	0	0	5110	0	1	16	1	1	40039	0	80000	80000	100	40043	40043	40043	40044	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	40043	300	0	0	0	0	0	0	1	3235	40027	0	16	0	25	163036	10	83026	80000	10	80000	80000	50	1839712	650958	40021	40442	40244	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40245	40446	3	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	0	0	5020	0	5	16	6	7	40040	80000	80000	10	40044	40050	40043	40050	40247
160024	40048	300	0	0	0	0	0	6	1	3885	40027	16	0	0	25	163029	10	82119	80000	10	80000	80000	50	1848580	650948	40021	40042	40049	19982	0	3	20023	160010	20	80000	80000	20	160000	160000	40043	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	41	80002	0	34	0	5020	0	7	16	6	5	40039	80000	80000	10	40043	40044	40044	40043	40043
160024	40042	300	0	0	0	0	0	3	0	2563	40028	16	16	0	25	162129	10	82119	80000	10	80000	80000	50	1839712	651177	40021	40048	40043	19982	0	3	20023	160010	20	80000	80000	20	160000	160000	40048	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	2	80002	2	34	0	5020	0	6	16	9	8	40039	80000	80000	10	40043	40043	40043	40043	40455
160024	40049	300	0	0	0	0	0	3	0	1660	40034	0	16	0	25	163029	10	83019	80000	10	80000	80000	50	1839832	651646	40023	40042	40042	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40042	40043	2	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	8	80002	2	34	0	5020	0	8	16	8	7	40039	80000	80000	10	40043	40044	40044	40043	40043
160024	40048	300	0	0	0	0	0	3	0	2119	40028	16	0	0	25	163666	10	83818	80000	10	80116	80000	50	1839712	649051	40021	40043	40043	19982	0	3	20028	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	0	80000	0	34	0	5020	0	8	16	7	6	40039	80000	80000	10	40043	40043	40044	40044	40863
160024	40042	300	0	0	0	0	6	3	1	2563	40035	16	0	0	25	163036	10	83026	80000	10	80000	80000	50	1839832	651657	40021	40042	40042	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	2	80002	0	34	0	5020	0	7	16	8	7	40039	80000	80000	10	40043	40043	40044	40050	40044
160024	40042	300	0	0	0	0	0	9	0	68	40028	0	16	0	25	162573	10	83652	80000	10	80000	80000	50	1839712	650948	40021	40043	40042	19982	0	17	20029	160010	20	80000	80000	20	160000	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	1	0	8	80000	2	0	0	5020	0	7	16	7	5	40040	80000	80000	10	40043	40251	40043	40044	40043
160024	40049	300	0	0	0	0	0	3	0	3649	40027	16	16	0	25	163029	10	83026	80000	10	80000	80000	50	1839808	649584	40021	40042	40042	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	0	80000	2	34	0	5020	0	5	16	6	7	40045	80000	80000	10	40043	40043	40044	40043	40050
160024	40043	300	0	1	0	0	0	3	0	3649	40027	16	16	0	25	162513	10	82384	80000	10	80000	80000	50	1839712	649058	40021	40042	40042	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	0	80002	0	34	0	5020	0	7	16	6	7	40039	80000	80000	10	40043	40049	40044	40043	40044
160024	40049	300	0	0	0	0	0	0	1	3656	40027	16	16	0	25	161918	10	83019	80000	10	80000	80000	50	1839808	649584	40021	40042	40042	19982	0	3	20022	160010	20	80000	80000	20	160000	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	2	34	96	0	80002	0	0	2	80002	2	34	0	5038	0	7	16	7	7	40039	80000	80000	10	40043	40043	40044	40044	40049

STP (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations