Firestorm: STP (post-index, D) measurements

Code:

  stp d0, d1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
9006	1166	9	0	1	0	5	12	0	25	0	1151	24	1	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1004	0	24	2	30	1000	1	22	12	0	1030	24	517	11	16	7	7	1163	1000	1	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	3	30	1	0	0	1151	0	1	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	24	1	39	1000	0	32	8	3	1014	28	516	6	16	7	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	6	3	14	1	18	0	1151	4	1	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1012	0	44	1	27	1000	0	36	36	0	1028	28	517	6	16	7	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	3	14	1	10	0	1151	6	0	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	20	1	20	1000	1	14	8	0	1014	44	517	7	16	7	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	6	3	14	1	10	0	1151	10	1	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1022	0	20	1	22	1000	2	22	24	0	1022	28	516	7	16	5	5	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	4	14	1	14	0	1151	14	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	24	1	14	1000	0	14	8	0	1014	28	517	7	16	8	8	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	0	12	4	16	1	10	0	1151	4	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	20	0	0	1000	0	0	0	0	1000	28	517	7	16	7	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	3	14	1	10	0	1151	4	2	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	20	2	14	1002	0	14	8	0	1014	20	515	7	16	7	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	3	14	1	10	0	1151	4	2	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1030	0	48	6	30	1000	0	30	24	0	1022	28	516	6	16	6	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	6	3	14	1	10	0	1151	10	0	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	24	1	22	1001	0	36	20	3	1030	36	517	7	16	7	7	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167

Test 2: Latency 3->3

Code:

  stp d0, d1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	37	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20224	10040	75	1	0	1	0	0	10272	53	2274	1	1664	96	7	4	212	10025	2218	0	189	236	31	25	30351	10100	10117	10000	10100	10000	10000	543994	468848	80539	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12477	14	1411	1538	0	1521	10968	1489	0	2493	50	4569	12516	23	640	0	0	710	1	16	1	1	10037	10000	215	4	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	0	0	0	0	0	10497	40	2308	1	1672	136	0	0	932	10025	2228	0	197	236	18	25	30122	10100	10171	10000	10100	10000	10000	543974	468848	80449	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12469	0	1572	1519	0	1484	10979	1526	0	2477	50	4582	12501	28	741	0	0	710	1	16	1	1	10037	10000	226	3	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	0	0	0	0	0	10329	57	2300	1	1664	111	2	1	776	10025	2228	0	232	196	25	25	30237	10100	10278	10000	10100	10000	10000	544002	468848	80296	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	0	1669	1496	0	1502	10990	1512	0	2497	50	4638	12497	25	630	0	0	710	1	16	1	1	10037	10000	395	6	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	0	0	0	0	0	10452	44	2263	1	1496	206	2	0	944	10025	2263	0	257	216	27	25	30270	10100	10132	10000	10100	10000	10000	543994	468848	80484	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12497	0	1601	1495	0	1475	10978	1513	0	2453	50	4548	12511	27	657	0	0	710	1	16	1	1	10037	10000	273	6	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	76	0	0	0	0	0	10317	62	2297	1	1592	135	3	0	716	10025	2236	0	187	243	20	25	30221	10100	10121	10000	10100	10000	10000	543978	468848	80284	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12489	0	1652	1508	0	1525	10990	1504	0	2481	50	4576	12504	29	610	0	0	710	1	16	1	1	10037	10000	293	5	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	0	0	0	0	0	10302	49	2263	1	1512	171	2	0	944	10025	2256	2	206	217	25	25	30203	10100	10168	10000	10100	10000	10000	543971	468848	80387	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	0	1622	1488	0	1464	11003	1503	0	2481	50	4498	12514	18	747	0	0	710	1	16	1	1	10037	10000	216	3	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	0	0	0	0	0	10374	50	2302	1	2232	77	8	0	212	10025	2168	0	215	187	37	25	30226	10100	10138	10000	10100	10000	10000	543994	468848	80785	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	5	1382	1697	0	1702	10797	1481	2	2493	50	4578	12509	34	632	0	2	710	1	16	1	1	10037	10000	318	9	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	1	0	0	0	0	10602	50	2186	1	2216	96	6	3	212	10025	2168	0	180	212	24	25	30212	10100	10208	10000	10100	10000	10000	543998	468848	80382	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12469	5	1485	1628	0	1696	10826	1501	0	2477	50	4594	12496	25	685	0	0	710	1	16	1	1	10037	10000	149	3	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	1	0	0	0	0	10563	44	2200	1	2216	241	5	0	212	10025	2251	0	208	196	32	25	30236	10100	10132	10000	10100	10000	10000	543994	468848	80409	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12469	5	1442	1655	0	1697	10816	1536	0	2477	50	4584	12491	31	782	0	0	710	1	16	1	1	10037	10000	268	7	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	1	0	0	0	0	10656	55	2207	1	2216	115	6	0	212	10025	2147	0	207	219	24	25	30221	10100	10123	10000	10100	10000	10000	543991	468848	80490	10016	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	5	1461	1670	0	1711	10840	1512	0	2469	50	4651	12497	24	649	0	0	710	1	16	1	1	10037	10000	240	1	1	10000	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	37	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20044	10040	75	1	0	1	10317	95	2274	1	1720	189	5	1	724	10025	2223	0	207	259	28	25	30271	10010	10662	10000	10010	10000	10000	543365	468848	80939	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	11	1585	1591	0	1566	10932	1493	0	2489	50	4634	12517	36	674	0	1	640	0	3	16	3	3	10037	10000	339	3	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	2	10269	71	2275	1	1720	298	4	0	724	10025	2236	0	249	243	26	25	30020	10010	10432	10000	10010	10000	10000	543277	468848	82023	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12481	16	1538	1577	0	1598	10952	1497	0	2480	50	4595	12496	44	633	7	2	640	0	2	16	2	2	10037	10000	281	3	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	1	0	0	10284	61	2282	1	1704	217	4	0	716	10025	2222	0	233	251	56	25	30019	10010	10305	10000	10010	10000	10000	543345	468848	80710	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12481	4	1790	1548	0	1585	10953	1519	0	2489	50	4570	12512	48	706	7	4	640	0	2	16	2	3	10037	10000	250	4	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	2	0	10203	91	2275	1	1704	273	8	0	716	10025	2230	0	229	244	26	25	30548	10010	10257	10000	10010	10000	10000	543397	468848	80678	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	22	1678	1594	0	1580	10931	1524	2	2497	50	4609	12515	41	700	7	4	640	0	3	16	3	3	10037	10000	257	1	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	2	2	10173	101	2266	1	1704	222	9	0	724	10025	2236	0	234	253	28	25	30212	10010	10228	10000	10010	10000	10000	543389	468848	81642	1	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12497	11	1620	1570	0	1556	10935	1552	2	2480	50	4532	12507	51	769	7	0	640	0	3	16	2	2	10037	10000	272	10	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	2	0	10269	66	2268	1	1704	536	6	0	724	10025	2236	0	275	235	37	25	30272	10010	10432	10000	10010	10000	10000	543329	468848	81630	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12472	4	1496	1577	0	1597	10921	1562	1	2481	50	4560	12501	37	575	0	2	640	0	3	16	3	3	10037	10000	260	6	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	0	10281	52	2253	1	1696	305	2	2	716	10025	2229	0	207	241	31	25	30026	10010	10018	10000	10010	10000	10000	543341	468848	80775	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	13	1611	1570	0	1582	10945	1488	4	2468	50	4651	12523	39	718	0	0	640	0	2	16	3	3	10037	10000	345	15	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	76	2	0	0	10350	64	2262	1	1696	258	4	0	724	10025	2216	0	240	248	25	25	30204	10010	10012	10000	10010	10000	10000	543261	468848	80036	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12478	15	1597	1558	0	1577	10941	1531	1	2465	50	4612	12521	51	698	0	2	640	0	2	16	3	3	10037	10000	218	8	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	0	10395	63	2274	1	1696	235	11	0	724	10025	2214	0	222	248	46	25	30322	10010	10552	10000	10010	10000	10000	543337	468848	80732	1	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12498	4	1538	1548	0	1579	10935	1513	0	2473	50	4644	12519	42	774	7	0	640	0	2	16	3	3	10037	10000	327	4	0	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	2	10515	82	2260	1	1704	322	6	0	724	10025	2237	0	248	212	35	25	30193	10010	10017	10000	10010	10000	10000	543341	468848	80907	0	0	10021	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12488	13	1577	1569	0	1571	10956	1539	6	2480	50	4575	12512	44	605	7	4	640	0	2	16	3	3	10037	10000	247	4	0	10000	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  stp d0, d1, [x6], #0x10
  stp d0, d1, [x7], #0x10
  stp d0, d1, [x8], #0x10
  stp d0, d1, [x9], #0x10
  stp d0, d1, [x10], #0x10
  stp d0, d1, [x11], #0x10
  stp d0, d1, [x12], #0x10
  stp d0, d1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5019

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160224	40192	302	6	6	6	10425	42	2285	1	1712	3674	11	264	40131	2236	797	551	46	25	243474	80110	82841	80000	80112	80012	80006	400583	1847236	643193	0	2	40134	40134	40207	20079	0	6	20124	240131	200	80016	80016	200	160032	160032	40123	40108	1	1	80201	100	99	100	100	80000	80000	100	82518	36	2029	2449	11	2487	80036	1497	10	2516	510	4587	82510	47	1747	14	8	1	1	1	5117	0	16	0	0	40196	80010	80000	80000	80100	40168	40168	40117	40172	40142
160204	40117	301	5	0	0	10233	54	2285	1	1496	3331	8	488	40107	2252	802	401	49	25	241523	80110	82900	80000	80116	80012	80007	400583	1844442	651426	0	2	40120	40119	40154	20043	0	6	20089	240140	200	80016	80016	200	160032	160032	40170	40181	1	1	80201	100	99	100	100	80000	80000	100	82518	36	1470	2452	5	2502	80035	1527	0	2492	510	4537	82509	39	2055	14	0	1	1	1	5117	0	16	0	0	40135	80010	80000	80000	80100	40131	40167	40138	40164	40156
160204	40125	300	4	4	0	10245	72	2324	1	1464	5059	14	520	40140	2231	740	801	46	25	241638	80102	81228	80000	80100	80000	80000	400531	1844392	648822	0	2	40141	40136	40120	20041	0	3	20086	240100	200	80000	80000	200	160000	160000	40113	40148	1	1	80201	100	99	100	100	80000	80000	100	82506	32	1489	2443	6	2498	80053	1536	0	2504	510	4711	82486	24	1868	14	4	0	0	0	5110	1	16	1	1	40161	80002	80000	80000	80100	40178	40128	40169	40180	40102
160204	40200	300	4	4	0	10218	83	2268	1	1456	3049	11	520	40134	2238	676	649	47	25	244278	80102	82942	80000	80100	80127	80000	400531	1843216	650408	0	2	40176	40198	40151	20202	0	3	20108	240100	200	80000	80000	200	160000	160000	40183	40111	1	1	80201	100	99	100	100	80000	80000	100	82509	36	1602	2460	117	2487	80048	1505	8	2468	510	4579	82474	37	1600	14	0	0	0	0	5110	1	16	1	1	40118	80002	80000	80000	80100	40140	40190	40165	40243	40117
160204	40138	301	4	0	4	10602	59	2271	1	1704	3990	11	264	40148	2251	758	419	36	25	241071	80102	83898	80000	80100	80000	80000	400531	1843936	643569	0	2	40083	40117	40158	20032	0	3	20100	240100	200	80000	80000	200	160000	160000	40150	40140	1	1	80201	100	99	100	100	80000	80000	100	82514	28	1578	2435	5	2481	80035	1495	0	2468	510	4619	82505	25	1382	14	0	0	0	0	5110	1	17	1	1	40149	80002	80000	80000	80100	40130	40137	40173	40135	40147
160204	40160	300	4	0	4	10233	62	2279	1	1672	2624	6	288	40118	2290	475	358	49	25	244036	80102	84101	80000	80100	80000	80000	400531	1844800	648521	0	2	40119	40142	40155	20067	0	3	20156	240100	200	80000	80000	200	160000	160000	40133	40127	1	1	80201	100	99	100	100	80000	80000	100	82495	36	1551	2461	20	2503	80066	1500	5	2492	254	4735	82497	51	2349	14	0	0	0	0	5110	1	17	1	1	40136	80002	80000	80000	80100	40135	40160	40131	40153	40155
160204	40191	301	5	0	5	10437	57	2232	1	1960	2587	6	264	40148	2212	536	371	25	25	241079	80102	82949	80000	80100	80000	80000	400531	1844992	651333	0	2	40095	40173	40130	20029	0	3	20112	240100	200	80000	80000	200	160000	160000	40125	40113	1	1	80201	100	99	100	100	80000	80000	100	82496	23	1624	2467	16	2475	80036	1513	0	2476	254	4581	82501	44	1938	14	0	0	0	0	5110	1	17	1	1	40165	80002	80000	80000	80100	40164	40142	40157	40156	40146
160204	40184	300	4	4	0	10392	81	2239	1	1952	1416	9	264	40080	2233	627	388	50	25	242986	80102	81235	80000	80100	80000	80000	400531	1845904	650017	0	2	40112	40141	40185	20053	0	3	20087	240100	200	80000	80000	200	160000	160000	40167	40153	1	1	80201	100	99	100	100	80000	80000	100	82510	28	2098	2447	1	2500	80038	1492	4	2484	254	4689	82519	56	2710	14	0	0	0	0	5110	1	17	1	1	40120	80002	80000	80000	80100	40175	40140	40159	40189	40155
160204	40163	300	4	4	4	10383	63	2232	1	1952	3356	11	264	40087	2212	803	435	66	25	241113	80102	82770	80000	80100	80000	80000	400531	1846240	649682	0	2	40141	40179	40122	20212	0	3	20119	240100	200	80000	80000	200	160000	160000	40132	40136	1	1	80201	100	99	100	100	80000	80000	100	82482	36	1427	2457	0	2508	80043	1512	0	2492	254	4610	82491	44	1606	14	4	0	0	0	5110	1	16	1	1	40154	80002	80000	80000	80100	40139	40161	40121	40119	40112
160204	40126	300	4	0	0	10491	87	2246	1	1968	2789	10	264	40101	2212	689	640	59	25	243867	80102	81400	80000	80100	80000	80000	400531	1843360	645052	0	2	40111	40133	40186	20004	0	3	20109	240100	200	80000	80000	200	160000	160000	40156	40133	1	1	80201	100	99	100	100	80000	80000	100	82498	28	1854	2432	4	2493	80045	1506	4	2499	254	4630	82471	53	1922	14	3	0	0	0	5110	1	16	1	1	40133	80002	80000	80000	80100	40146	40124	40152	40124	40197

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5016

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	20	22	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	67	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160044	40197	301	3	3	3	0	10347	44	2310	1	1704	107	4	320	40123	2251	661	511	51	25	243824	80012	82448	80000	80010	80000	80000	400081	1843696	654649	1	5	2	40075	40102	40096	20024	0	3	20077	240010	20	80000	80000	20	160000	160000	40163	40138	1	1	80021	10	9	10	10	80000	80000	10	82498	20	1175	2479	6	2492	80049	1520	0	2484	510	4739	82505	40	1662	14	0	5020	5	3	15	16	0	0	17	17	40123	80002	80000	80000	80010	40121	40131	40141	40128	40160
160024	40137	300	2	2	0	0	10257	78	2310	1	1248	3215	7	320	40071	2239	507	621	41	25	244452	80012	80526	80000	80010	80000	80000	400081	1844032	640285	1	5	2	40093	40116	40116	20053	0	3	20130	240010	20	80000	80000	20	160000	160000	40137	40144	1	1	80021	10	9	10	10	80000	80000	10	82522	16	946	2467	5	2470	80029	1519	0	2496	746	4606	82521	45	1447	14	0	5020	5	3	8	16	0	0	9	17	40120	80002	80000	80000	80010	40135	40122	40114	40145	40133
160024	40102	300	2	0	0	0	9756	56	2348	1	1456	104	6	252	40125	2307	376	356	41	25	240163	80012	83762	80000	80010	80000	80000	400081	1844728	649458	1	5	2	40075	40139	40159	20050	0	3	20105	240010	20	80000	80000	20	160000	160000	40135	40119	1	1	80021	10	9	10	10	80000	80000	10	82510	20	1648	2465	6	2490	80058	1532	4	2480	510	4559	82513	33	1386	14	2	5020	5	3	17	16	0	0	17	17	40132	80002	80000	80000	80010	40113	40104	40138	40172	40143
160024	40134	300	3	3	0	0	10503	45	2246	1	1976	1327	9	264	40159	2219	729	831	41	25	244283	80012	83510	80000	80010	80000	80000	400081	1844224	648797	1	5	2	40270	40152	40164	20065	0	3	20140	240010	20	80000	80000	20	160000	160000	40169	40162	1	1	80021	10	9	10	10	80000	80000	10	82510	36	1886	2451	9	2476	80034	1538	4	2492	252	4582	82525	39	1952	14	8	5020	5	3	8	16	0	0	8	17	40103	80002	80000	80000	80010	40168	40125	40161	40148	40128
160024	40115	301	4	4	0	0	10506	69	2239	1	1976	666	8	264	40127	2233	506	610	65	25	243273	80012	80496	80000	80010	80000	80000	400081	1844584	641384	1	5	2	40161	40140	40131	20056	0	3	20139	240010	20	80000	80000	20	160000	160000	40154	40160	1	1	80021	10	9	10	10	80000	80000	10	82514	32	1740	2450	8	2507	80051	1503	0	2468	254	4586	82512	48	1875	14	8	5020	5	3	17	16	0	0	17	8	40146	80002	80000	80000	80010	40122	40108	40112	40139	40115
160024	40128	300	3	3	3	0	10233	46	2311	1	1632	3606	5	296	40120	2261	673	466	59	25	244083	80012	84359	80000	80010	80000	80000	400081	1844344	650553	1	5	2	40100	40100	40149	20058	0	3	20098	240010	20	80000	80000	20	160000	160000	40136	40163	1	1	80021	10	9	10	10	80000	80000	10	82506	27	1629	2452	14	2488	80041	1515	9	2484	510	4659	82525	50	1348	14	3	5020	5	3	9	16	0	0	17	8	40095	80002	80000	80000	80010	40139	40083	40132	40182	40125
160024	40126	301	3	3	3	0	10347	74	2274	1	1464	532	6	252	40128	2290	649	605	31	25	240797	80012	80036	80000	80010	80000	80000	400081	1844272	642401	1	5	2	40099	40168	40117	20057	0	3	20104	240010	20	80000	80000	20	160000	160000	40154	40130	1	1	80021	10	9	10	10	80000	80000	10	82513	24	933	2478	8	2484	80029	1496	0	2480	508	4583	82533	65	1537	14	3	5020	5	4	18	16	0	0	9	17	40123	80002	80000	80000	80010	40167	40125	40157	40135	40150
160024	40161	301	3	0	0	0	10242	49	2317	1	1456	489	9	520	40129	2262	523	578	63	25	242914	80012	81097	80000	80010	80000	80000	400081	1843576	648739	1	5	2	40092	40116	40099	20070	0	3	20128	240010	20	80000	80000	20	160000	160000	40123	40155	1	1	80021	10	9	10	10	80000	80000	10	82502	24	1687	2464	18	2482	80034	1507	0	2492	508	4673	82512	31	1366	14	3	5020	5	4	17	16	0	0	17	17	40139	80002	80000	80000	80010	40178	40130	40185	40177	40074
160024	40107	301	3	3	3	0	10302	65	2246	1	1960	982	5	264	40116	2205	518	633	65	25	243566	80012	82436	80000	80010	80000	80000	400081	1843624	651614	1	5	2	40064	40114	40150	20066	0	3	20116	240010	20	80000	80000	20	160000	160000	40151	40102	1	1	80021	10	9	10	10	80000	80000	10	82506	23	1426	2480	2	2493	80052	1547	6	2468	254	4625	82504	45	1626	14	6	5020	5	4	17	16	0	0	18	7	40110	80002	80000	80000	80010	40126	40114	40130	40137	40156
160024	40147	300	4	4	0	0	10554	62	2252	1	1968	4300	8	264	40104	2219	691	659	43	25	241299	80012	83267	80000	80010	80000	80000	400081	1843648	648351	1	5	2	40146	40214	40155	20067	0	3	20104	240010	20	80000	80000	20	160000	160000	40140	40129	1	1	80021	10	9	10	10	80000	80000	10	82512	27	893	2453	6	2500	80055	1520	0	2492	510	4538	82509	46	1093	14	0	5020	5	4	6	16	0	0	17	17	40185	80002	80000	80000	80010	40138	40123	40129	40153	40125

STP (post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations