Firestorm: STP (post-index, Q) measurements

Code:

  stp q0, q1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
9005	1165	9	1	1	0	0	0	3	28	1	0	6	0	1150	0	0	0	0	25	3000	1000	2000	1000	2000	5999	11902	1	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2016	24	95	5	0	20	2000	3	0	26	22	0	2026	0	95	0	514	5	16	5	4	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	8	0	0	0	0	9	2	14	0	0	0	0	1150	0	23	0	0	25	3000	1000	2000	1000	2000	5999	11924	1	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2032	0	87	5	0	26	2000	1	0	49	14	0	2028	0	55	0	514	5	16	5	5	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	0	0	0	0	2	24	1	0	10	12	1150	0	1	0	0	25	3000	1000	2000	1000	2000	5999	11894	0	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2040	0	79	7	0	16	2000	0	0	14	16	3	2032	0	71	0	514	3	16	5	3	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	0	0	0	0	3	12	0	0	14	24	1150	43	0	6	0	25	3000	1000	2000	1000	2000	5999	11902	0	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2032	0	63	3	0	32	2000	0	0	30	18	0	2032	0	98	0	514	4	16	4	4	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	1	0	0	6	3	0	0	24	4	0	1150	0	0	0	0	25	3000	1000	2000	1000	2000	5999	11902	1	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2036	0	111	0	0	40	2000	0	0	24	14	3	2036	0	63	0	514	4	16	4	4	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	0	0	0	6	4	28	1	0	15	16	1150	21	0	0	0	25	3000	1000	2000	1000	2000	5999	11924	0	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2020	0	87	7	0	16	2002	0	0	22	16	0	2000	0	87	0	513	3	16	2	2	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	0	0	0	0	2	14	1	0	10	12	1150	15	8	0	0	25	3000	1000	2000	1000	2000	5999	11902	1	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2024	0	79	4	0	24	2000	0	0	18	16	0	2026	0	79	0	514	5	16	5	5	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	1	0	0	0	3	0	0	0	4	12	1150	13	0	0	0	25	3000	1000	2000	1000	2000	5999	11889	0	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2024	0	106	10	0	24	2000	0	0	44	12	0	2024	0	87	0	513	4	16	4	5	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	8	0	0	0	0	0	2	22	0	0	10	4	1150	5	3	3	0	25	3000	1000	2000	1000	2000	5999	11902	0	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2022	0	87	3	0	20	2000	0	0	22	14	0	2024	0	71	0	514	4	16	4	2	1162	1000	0	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	0	0	0	0	0	3	32	1	24	14	16	1150	13	16	7	0	25	3000	1000	2000	1000	2000	5999	11994	0	1140	1165	1165	0	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2030	0	63	0	0	22	2000	0	0	0	0	0	2044	0	95	0	513	3	16	4	4	1162	1000	0	2000	1000	1166	1166	1166	1166	1166

Test 2: Latency 3->3

Code:

  stp q0, q1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0279

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20223	11595	86	2	2	0	0	0	10599	109	2257	1	1720	5	0	980	11543	2250	0	243	247	128	25	30100	10100	20000	10100	20000	79021	469096	1	10204	11505	11546	8921	3	7662	30100	200	20000	200	40000	10285	10252	1	1	10201	100	99	100	100	10000	10000	100	22493	27	1698	2030	45	2068	20489	1547	3	2489	50	4598	22525	53	1263	0	4	710	2	16	2	2	10188	10000	18	0	1	20000	10100	10245	10161	10189	10218	10255
20204	10200	77	1	1	0	0	0	10479	95	2313	1	1496	5	0	720	10201	2273	1	322	270	60	25	30100	10100	20000	10100	20000	79156	466096	1	10164	11484	11485	8885	3	8976	30100	200	20000	200	40000	11473	11533	1	1	10201	100	99	100	100	10000	10000	100	22482	6	1542	2019	49	2044	20531	1545	1	2501	50	4601	22528	48	1234	0	1	710	2	16	2	2	10293	10000	38	0	1	20000	10100	10189	10242	10171	10234	10254
20204	10178	76	1	1	1	0	0	10260	78	2271	1	1464	3	0	944	11461	2254	1	252	273	147	25	30100	10100	20000	10100	20000	75488	528304	1	11561	10194	10197	7641	3	7664	30100	200	20000	200	40000	11510	11485	1	1	10201	100	99	100	100	10000	10000	100	22497	5	1047	2395	29	2460	20084	1508	1	2489	50	4779	22551	48	1287	0	1	710	2	16	2	2	11522	10000	74	0	5	20000	10100	11481	11557	11499	11530	11545
20204	11477	86	1	0	1	0	0	10227	98	2299	1	1464	3	0	956	10171	2267	0	255	285	100	25	30100	10100	20000	10100	20000	79208	465928	1	10163	11521	11570	8977	3	8944	30100	200	20000	200	40000	11519	11539	1	1	10201	100	99	100	100	10000	10000	100	22493	9	1545	1993	24	2034	20484	1534	4	2477	50	4694	22518	46	1235	0	4	710	2	16	2	2	11567	10000	87	0	3	20000	10100	11504	11470	11510	11531	11576
20204	11487	87	2	0	0	0	0	10536	84	2320	1	1480	6	0	980	10176	2274	0	279	248	120	25	30100	10100	20000	10100	20000	79337	470152	1	10180	11561	11504	8913	3	8990	30100	200	20000	200	40000	11595	11536	1	1	10201	100	99	100	100	10000	10000	100	22493	9	1441	2016	15	2001	20535	1534	0	2489	50	4631	22518	34	1254	0	0	710	2	16	2	2	10197	10000	27	1	2	20000	10100	10163	10240	10234	10263	10243
20204	10233	76	1	0	1	0	0	10347	50	2271	1	1712	5	0	760	11486	2221	0	208	288	98	25	30100	10100	20000	10100	20000	75575	527584	0	11520	10215	10233	7659	3	7639	30100	200	20000	200	40000	10210	10212	1	1	10201	100	99	100	100	10000	10000	100	22487	21	1140	2442	24	2451	20091	1551	0	2473	50	4586	22516	62	1141	0	0	710	2	16	2	2	11578	10000	69	1	8	20000	10100	10322	10207	10252	10172	10240
20204	10215	77	2	2	0	0	0	10464	45	2328	1	1496	8	0	940	11542	2261	0	257	220	120	25	30100	10100	20000	10100	20000	79104	467728	1	10150	11460	11456	8968	3	8927	30100	200	20000	200	40000	11537	11521	1	1	10201	100	99	100	100	10000	10000	100	22495	26	1594	2011	19	2056	20527	1508	2	2485	50	4618	22521	51	1402	0	1	710	2	16	2	2	11502	10000	101	0	3	20000	10100	11487	11558	11551	11595	11455
20204	11539	86	1	0	0	0	0	10431	91	2286	1	1472	8	0	716	11530	2253	0	196	281	119	25	30100	10100	20000	10100	20000	75576	530080	1	11464	10278	10226	7658	3	7688	30100	200	20000	200	40000	10173	10196	1	1	10201	100	99	100	100	10000	10000	100	22493	9	1295	2436	13	2473	20087	1503	0	2485	50	4653	22540	72	1145	0	0	710	2	16	2	2	10248	10000	27	0	1	20000	10100	10213	10185	10204	10190	10247
20204	10217	77	2	0	2	0	0	10599	62	2267	1	1472	13	0	880	11466	2274	0	231	219	182	25	30100	10100	20000	10100	20000	75576	526816	1	11514	10215	10247	7616	3	7682	30100	200	20000	200	40000	10226	10189	1	1	10201	100	99	100	100	10000	10000	100	22507	12	1347	2406	18	2456	20102	1550	0	2489	50	4659	22517	57	1354	0	0	710	2	16	2	2	11484	10000	27	14	3	20000	10100	10233	10199	10247	10212	10257
20204	10200	77	3	0	0	0	0	10242	56	2313	1	1512	6	0	804	11483	2267	0	245	207	197	25	30100	10100	20000	10100	20000	79179	468928	0	10198	11544	11592	8929	3	8995	30100	200	20000	200	40000	11542	11520	1	1	10201	100	99	100	100	10000	10000	100	22501	16	1537	1995	33	2019	20529	1531	2	2485	50	4540	22509	34	1140	0	6	710	2	16	2	2	10208	10000	32	0	1	20000	10100	10257	10258	10214	10207	10233

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0349

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	20	22	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20043	10220	77	1	0	1	0	10224	59	2268	1	1696	7	0	724	10247	2234	0	294	269	132	25	30010	10010	20000	10010	20000	75170	524656	1	11398	11433	11411	8870	3	7765	30010	20	20000	20	40000	10279	10273	1	1	10021	10	9	10	10	10000	10000	10	22488	4	1584	2068	14	2146	20460	1503	0	2489	50	4562	22574	59	1257	0	0	0	640	3	16	3	2	11364	10000	78	0	1	20000	10010	10238	10219	10280	10236	10238
20024	10326	76	1	0	0	0	10194	63	2268	1	1704	7	0	724	10184	2219	0	327	322	132	25	30010	10010	20000	10010	20000	77846	470104	0	10294	10217	10233	7650	3	7727	30010	20	20000	20	40000	10246	10220	1	1	10021	10	9	10	10	10000	10000	10	22482	4	1346	2401	25	2336	20108	1515	1	2489	50	4572	22546	65	1175	14	0	0	640	2	16	3	3	10251	10000	56	1	0	20000	10010	10249	10221	10289	10252	10285
20024	10219	76	2	0	0	0	10092	81	2275	1	1680	5	0	724	11380	2213	0	232	290	129	25	30010	10010	20000	10010	20000	75021	526000	0	11413	11437	11395	8803	3	8883	30010	20	20000	20	40000	10281	10337	1	1	10021	10	9	10	10	10000	10000	10	22484	38	1284	2397	73	2433	20153	1486	2	2485	50	4624	22547	64	975	14	0	0	640	3	16	2	2	10320	10000	53	1	1	20000	10010	10273	10206	10247	10234	10192
20024	10277	77	2	2	2	0	10329	137	2260	1	1712	5	0	724	10210	2220	0	310	385	106	25	30010	10010	20000	10010	20000	75321	473516	1	10235	10327	10320	7792	3	7742	30010	20	20000	20	40000	10285	10223	1	1	10021	10	9	10	10	10000	10000	10	22495	20	1593	2072	37	2079	20428	1495	2	2479	50	4653	22504	51	1073	14	0	0	640	3	16	3	3	11415	10000	75	0	2	20000	10010	11435	11445	11453	11428	11431
20024	11439	85	2	0	0	0	9981	96	2234	1	1696	9	0	716	11472	2229	1	265	287	182	25	30010	10010	20000	10010	20000	73741	527636	0	11424	11437	11410	8843	3	8938	30010	20	20000	20	40000	11414	11361	1	1	10021	10	9	10	10	10000	10000	10	22473	20	1524	2123	73	2107	20415	1502	0	2481	50	4598	22508	66	957	0	0	0	640	3	16	2	2	10262	10000	36	2	0	20000	10010	10293	10275	10227	10260	10272
20024	10202	77	1	1	1	0	10134	74	2268	1	1704	5	0	724	11396	2193	0	269	294	117	25	30010	10010	20000	10010	20000	75117	523120	0	11400	11387	11477	8847	3	8878	30010	20	20000	20	40000	11414	11496	1	1	10021	10	9	10	10	10000	10000	10	22489	4	1639	2033	49	2103	20432	1544	1	2473	50	4583	22526	60	1201	0	0	0	640	2	16	3	3	11429	10000	67	5	0	20000	10010	11444	11385	11404	11367	11388
20024	11442	85	1	0	0	0	10230	93	2268	1	1696	4	0	716	10209	2229	0	288	270	106	25	30010	10010	20000	10010	20000	77646	470608	0	10225	10227	10184	7720	3	7736	30010	20	20000	20	40000	10236	10213	1	1	10021	10	9	10	10	10000	10000	10	22483	20	1004	2387	34	2404	20109	1534	0	2481	50	4610	22536	55	1164	0	1	0	640	3	16	3	2	10268	10000	51	4	1	20000	10010	10261	10217	10194	10344	10305
20024	10235	76	1	1	0	0	10188	82	2256	1	1712	3	0	716	10237	2227	0	254	332	102	25	30010	10010	20000	10010	20000	78013	468112	1	11381	11403	11433	8850	3	8944	30010	20	20000	20	40000	11410	11422	1	1	10021	10	9	10	10	10000	10000	10	22471	4	1556	2042	36	2055	20438	1487	1	2489	50	4532	22520	43	1186	0	0	0	640	2	16	3	3	11411	10000	58	0	0	20000	10010	11423	11386	11445	11411	11397
20024	11438	85	1	0	0	0	10059	68	2267	1	1704	3	0	716	11390	2228	0	323	309	139	25	30010	10010	20000	10010	20000	78001	470584	0	10271	10284	10321	7670	3	7762	30010	20	20000	20	40000	10266	10289	1	1	10021	10	9	10	10	10000	10000	10	22479	7	1513	2078	25	2073	20475	1515	0	2465	50	4590	22523	61	1044	0	2	0	640	3	16	3	3	10295	10000	58	0	0	20000	10010	10248	10300	10291	10287	10284
20024	10223	76	1	0	0	0	10275	72	2273	1	1496	5	0	704	11431	2202	0	305	326	132	25	30010	10010	20000	10010	20000	73734	526532	0	11356	11483	11457	8855	3	8880	30010	20	20000	20	40000	10239	10283	1	1	10021	10	9	10	10	10000	10000	10	22486	18	1326	2366	24	2445	20139	1510	0	2463	50	4603	22505	70	1093	27	2	0	640	3	16	3	2	10279	10000	66	1	0	20000	10010	11494	11396	11436	11440	11445

Test 3: throughput

Count: 8

Code:

  stp q0, q1, [x6], #0x10
  stp q0, q1, [x7], #0x10
  stp q0, q1, [x8], #0x10
  stp q0, q1, [x9], #0x10
  stp q0, q1, [x10], #0x10
  stp q0, q1, [x11], #0x10
  stp q0, q1, [x12], #0x10
  stp q0, q1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160223	80244	601	3	0	3	3	9813	205	2293	1	1488	10	264	80323	2221	791	1004	71	25	240104	80104	160000	80100	160000	400511	3689869	1	4	80275	80314	80259	60155	3	60209	240100	200	160000	200	320000	80292	80226	1	1	80201	100	99	100	100	80000	80000	100	162466	27	2334	2423	10	2475	160206	1503	4	2468	504	4725	162619	129	1003	14	8	0	5110	1	16	1	1	80237	80004	160000	80100	80244	80236	80171	80309	80302
160204	80249	601	5	0	0	0	9714	278	2267	1	1960	15	260	80259	2258	601	1141	123	25	240104	80104	160000	80100	160000	400511	3690732	1	4	80209	80218	80307	60279	3	60220	240100	200	160000	200	320000	80311	80354	1	1	80201	100	99	100	100	80000	80000	100	162484	27	2629	2460	7	2473	160175	1512	8	2468	502	4751	162632	184	2936	14	4	0	5110	1	16	1	1	80283	80004	160000	80100	80260	80221	80290	80253	80244
160204	80346	601	4	4	0	0	9861	307	2293	2	1488	17	264	80320	2229	1095	822	64	25	240104	80104	160000	80100	160000	400511	3689796	1	4	80270	80345	80365	60160	3	60294	240100	200	160000	200	320000	80285	80286	1	1	80201	100	99	100	100	80000	80000	100	162519	29	2513	2387	12	2465	160208	1493	5	2476	258	4829	162610	161	1438	21	0	0	5110	1	16	1	1	80196	80004	160000	80100	80234	80285	80307	80317	80348
160204	80379	601	4	0	0	0	9939	257	2294	1	1704	19	228	80084	2269	972	1242	103	25	240104	80104	160000	80100	160000	400511	3693276	1	4	80204	80307	80288	60130	3	60238	240100	200	160000	200	320000	80284	80250	1	1	80201	100	99	100	100	80000	80000	100	162482	27	2209	2449	8	2466	160152	1526	8	2472	510	4752	162594	171	1731	14	0	0	5110	1	16	1	1	80282	80004	160000	80100	80275	80235	80372	80345	80248
160204	80337	601	3	0	0	0	9852	166	2343	1	1504	14	208	80179	2248	1298	687	57	25	240104	80104	160000	80100	160000	400511	3689604	1	4	80247	80337	80216	60214	3	60215	240100	200	160000	200	320000	80232	80296	1	1	80201	100	99	100	100	80000	80000	100	162485	26	2046	2414	5	2483	160192	1518	3	2478	498	4763	162627	154	2273	21	0	0	5110	1	16	1	1	80335	80004	160000	80100	80303	80254	80389	80302	80274
160204	80359	602	4	0	4	4	9984	304	2263	1	1480	17	268	80324	2269	973	980	76	25	240104	80104	160000	80100	160000	400511	3693158	1	4	80279	80209	80251	60190	3	60192	240100	200	160000	200	320000	80258	80275	1	1	80201	100	99	100	100	80000	80000	100	162486	27	1774	2410	3	2471	160168	1493	0	2472	510	4705	162618	218	2034	14	0	0	5110	1	16	1	1	80270	80004	160000	80100	80268	80241	80330	80311	80306
160204	80338	601	4	0	4	0	10089	283	2249	1	1480	12	224	80247	2265	793	1158	111	25	240104	80104	160000	80100	160000	400511	3692340	1	4	80193	80363	80334	60214	3	60317	240100	200	160000	200	320000	80343	80319	1	1	80201	100	99	100	100	80000	80000	100	162462	36	2507	2440	3	2465	160202	1659	0	2468	512	4811	162622	187	1963	14	8	0	5110	1	16	1	1	80294	80004	160000	80100	80258	80341	80270	80295	80327
160204	80324	602	4	0	4	0	10059	252	2293	1	1480	14	260	80313	2224	725	1349	62	25	240104	80104	160000	80100	160000	400511	3690780	1	4	80327	80262	80304	60184	3	60182	240100	200	160000	200	320000	80330	80330	1	1	80201	100	99	100	100	80000	80000	100	162501	35	2872	2399	2	2482	160193	1546	0	2476	276	4764	162663	165	2011	14	4	0	5110	1	16	1	1	80229	80004	160000	80100	80306	80357	80282	80330	80278
160204	80280	602	4	0	4	4	9792	328	2284	1	1504	13	284	80239	2473	966	845	87	25	240104	80104	160000	80100	160000	400511	3689292	1	4	80236	80231	80268	60288	3	60165	240100	200	160000	200	320000	80306	80265	1	1	80201	100	99	100	100	80000	80000	100	162490	29	2540	2397	2	2494	160184	1506	12	2466	258	4737	162664	157	2906	14	0	0	5110	1	16	1	1	80357	80004	160000	80100	80228	80298	80378	80275	80334
160204	80242	601	4	0	0	4	9837	207	2272	1	1712	14	260	80267	2232	976	656	310	25	240104	80104	160060	80100	160000	400511	3692810	1	4	80180	80234	80297	60282	3	60228	240100	200	160000	200	320000	80277	80285	1	1	80201	100	99	100	100	80000	80000	100	162488	29	2231	2416	3	2480	160162	1483	5	2484	258	4815	162615	144	1799	14	0	0	5110	1	16	1	1	80192	80004	160000	80100	80230	80284	80299	80299	80362

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0025

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160043	80131	601	0	1	1	0	1	0	0	9771	298	2281	1	0	0	1304	12	160	80226	2344	692	541	59	25	240014	80014	160000	80010	160000	400061	3688356	1	0	4	80125	80172	80252	60144	3	60248	240010	20	160000	20	320000	80174	80133	1	1	80021	10	9	10	10	80000	80000	10	162512	14	950	2406	7	2472	160116	1517	0	2505	194	4832	162567	144	1755	14	0	5022	0	0	3	16	1	1	2	80152	80004	160000	80010	80201	80289	80266	80206	80146
160024	80198	600	0	0	0	0	0	0	0	9813	87	2328	1	0	0	1000	11	212	80285	2255	985	615	54	25	240014	80014	160000	80010	160000	400061	3688040	0	0	4	80149	80240	80208	60121	3	60291	240010	20	160000	20	320000	80153	80194	1	1	80021	10	9	10	10	80000	80000	10	162497	0	1540	2460	8	2469	160169	1483	0	2474	176	4654	162627	201	2134	0	0	5022	0	0	1	16	1	1	2	80148	80004	160000	80010	80155	80210	80214	80212	80372
160024	80217	601	0	0	0	0	0	0	0	9702	217	2313	1	0	0	1248	12	160	80204	2241	773	1042	55	25	240014	80014	160000	80010	160000	400061	3693080	0	0	4	80168	80388	80289	60132	3	60177	240010	20	160000	20	320000	80310	80248	1	1	80021	10	9	10	10	80000	80000	10	162469	0	1613	2477	5	2455	160105	1520	0	2505	112	4673	162594	142	1482	0	0	5022	0	0	1	16	1	1	2	80217	80004	160000	80010	80234	80278	80285	80284	80154
160024	80179	601	0	1	0	0	0	0	0	9960	119	2310	1	0	0	1016	9	196	80252	2235	669	1337	46	25	240014	80014	160000	80010	160000	400061	3684032	1	0	4	80138	80158	80252	60153	3	60130	240010	20	160000	20	320000	80216	80232	1	1	80021	10	9	10	10	80000	80000	10	162494	0	970	2468	5	2469	160140	1666	0	2490	516	4682	162567	104	1009	0	1	5022	0	0	1	16	2	2	2	80238	80004	160000	80010	80203	80185	80169	80196	80126
160024	80127	601	0	0	0	0	0	0	0	9933	105	2296	1	0	0	1296	14	156	80261	2272	342	666	31	25	240014	80014	160000	80010	160000	400061	3687464	0	0	4	80164	80124	80225	60205	3	60212	240010	20	160000	20	320000	80219	80219	1	1	80021	10	9	10	10	80000	80000	10	162484	0	506	2478	1	2469	160137	1542	0	2478	286	4689	162605	152	2463	0	0	5022	0	0	1	16	1	1	2	80323	80004	160000	80010	80188	80170	80370	80155	80208
160024	80264	601	0	0	0	0	0	0	0	10038	134	2242	1	0	0	1272	10	176	80149	2305	780	870	50	25	240136	80014	160000	80010	160000	400061	3689480	1	0	4	80173	80151	80169	60094	3	60095	240010	20	160000	20	320000	80282	80315	1	1	80021	10	9	10	10	80000	80000	10	162485	0	1852	2445	3	2482	160118	1544	0	2476	514	4679	162565	148	1299	0	0	5022	0	0	1	16	1	1	2	80245	80004	160000	80010	80267	80333	80162	80283	80218
160024	80238	600	0	0	0	0	0	0	0	9768	159	2281	1	0	0	1264	8	292	80202	2221	1214	532	55	25	240014	80014	160000	80010	160000	400341	3685424	0	0	4	80115	80346	80199	60181	3	60256	240010	20	160000	20	320240	80189	80257	1	1	80021	10	9	10	10	80000	80000	10	162456	0	1709	2425	5	2507	160105	1540	0	2494	464	4700	162620	94	1085	0	0	5022	0	0	1	16	1	1	2	80252	80004	160000	80010	80158	80304	80180	80259	80112
160024	80246	601	0	0	0	0	0	0	0	9507	263	2343	1	0	0	1296	13	204	80213	2249	803	828	68	25	240014	80014	160000	80010	160000	400061	3692000	1	0	4	80129	80239	80180	60197	3	60251	240010	20	160000	20	320000	80161	80152	1	1	80021	10	9	10	10	80000	80000	10	162485	0	2321	2424	3	2462	160148	1544	0	2499	78	4681	162612	26	1702	0	0	5022	0	0	1	16	1	1	2	80194	80004	160000	80010	80155	80121	80232	80231	80178
160024	80232	602	1	0	0	0	1	20	19	12363	2084	2301	1	0	0	1688	11	356	82161	2204	1612	1280	1558	356	242334	81195	160960	81186	162160	405384	3753080	1	0	4	82823	83149	83166	61556	108	62693	243454	20	161920	20	320000	80299	80416	1	1	80021	10	9	10	10	80000	80000	10	162476	0	1545	2405	4	2472	161135	1513	0	2486	734	17502	163778	172	2245	0	0	5262	0	0	4	205	1	6	2	83041	81184	160000	80010	82974	82894	83027	82270	82840
160024	82326	623	0	0	0	0	0	17	21	12636	1996	2182	1	0	0	1296	8	212	83151	2187	1956	1637	1720	703	242450	81694	161080	81522	162916	406501	3838772	0	0	4	83167	83585	82636	62286	3	60265	240010	20	160000	20	320000	80248	80264	1	1	80021	10	9	10	10	80000	80000	10	162482	0	1847	2442	8	2494	160108	1547	0	2498	426	4684	162689	172	3575	0	0	5022	0	0	1	16	1	1	2	80338	80004	160000	80010	80331	80162	80347	80135	80274

STP (post-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations