Firestorm: STP (post-index, S) measurements

Code:

  stp s0, s1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
9006	1166	9	0	0	0	0	4	0	0	3	0	1151	0	0	3	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1031	55	20	0	19	1009	0	1	19	0	6	1014	0	28	0	0	512	0	2	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	1	0	4	38	1	0	0	1151	0	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	16	0	0	1000	0	0	0	0	0	1000	0	16	0	0	512	2	2	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	1	1	1	0	10	0	0	3	0	1151	7	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1019	18	20	0	13	1009	0	1	16	0	6	1000	6	20	6	1	511	0	2	16	2	2	1163	1000	1	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	0	1	6	8	14	1	17	0	1151	10	3	2	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1020	6	28	3	20	1010	0	1	19	24	6	1034	6	36	6	0	512	0	2	16	2	2	1163	1000	1	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	0	1	0	8	14	1	13	4	1151	4	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1007	7	28	0	0	1006	0	1	0	0	6	1000	6	32	6	0	511	0	1	16	2	2	1163	1000	2	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	1	1	0	9	0	0	3	0	1151	0	7	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	20	4	22	1004	0	0	23	16	0	1019	0	20	0	0	512	0	2	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	0	2	20	1	10	0	1151	4	1	2	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1012	0	28	0	28	1000	0	0	19	6	0	1032	0	16	0	0	511	0	1	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	3	14	1	10	0	1151	4	4	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1004	12	16	0	0	1001	0	0	25	12	0	1025	0	40	0	0	512	0	1	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	6	4	12	0	11	0	1151	10	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	20	1	19	1000	0	0	23	14	0	1022	0	24	0	0	511	0	2	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	1	1	1	0	9	14	1	19	0	1151	10	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	32	0	9	1003	0	0	25	0	0	1000	0	24	0	0	512	0	2	16	2	2	1163	1000	0	1000	1000	1000	1167	1167	1167	1167	1167

Test 2: Latency 3->3

Code:

  stp s0, s1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	20	22	29	37	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20224	10040	76	6	2	2	0	10344	78	2211	1	2208	83	3	0	212	10025	2158	224	225	27	25	30325	10100	10117	10000	10100	10000	10000	543951	468848	80429	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12491	12	2463	1527	0	1714	10956	1526	2	2481	150	4612	12496	74	843	0	4	710	1	16	1	1	10037	10000	426	13	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	2	2	0	10365	77	2204	1	2216	93	6	0	212	10025	2162	246	238	61	25	30179	10100	10075	10000	10100	10000	10000	543966	468848	80297	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12473	14	1443	1686	0	1693	10838	1485	6	2481	50	4580	12481	84	649	7	6	710	1	16	1	1	10037	10000	217	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	0	0	0	10599	162	2203	1	2208	90	7	0	212	10025	2134	250	224	33	25	30253	10100	10106	10000	10100	10000	10000	543903	468848	80563	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12487	19	1526	1568	0	1673	10818	1519	3	2473	50	4620	12491	42	769	7	3	710	1	16	1	1	10037	10000	391	2	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	5	3	0	0	10422	64	2218	4	2208	232	6	0	212	10025	2165	269	235	42	25	30227	10100	10112	10000	10100	10000	10000	543931	468848	80467	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12491	25	1569	1632	1	1600	10830	1469	3	2473	50	4571	12501	45	701	7	0	710	1	16	1	1	10037	10000	277	7	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	3	0	0	10287	77	2196	1	2216	73	9	0	212	10025	2180	213	229	99	25	30234	10100	10100	10000	10100	10000	10000	543916	468848	80702	10021	10040	10040	7424	3	7664	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12464	19	1569	1667	0	1680	10910	1498	3	2488	50	4558	12483	48	781	7	3	710	1	16	1	1	10037	10000	329	12	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	76	4	3	0	0	10233	87	2197	1	2208	84	5	0	212	10147	2156	243	266	51	25	30146	10100	10158	10000	10100	10000	10108	543938	468848	80254	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12487	18	1453	1675	0	1702	10832	1499	3	2480	50	4573	12486	50	743	7	0	710	1	16	1	1	10141	10095	262	5	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	3	3	0	10449	81	2204	1	2208	93	6	0	212	10150	2158	241	224	38	25	30246	10100	10170	10000	10100	10000	10000	543888	468848	80308	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	21	1563	1659	0	1708	10833	1514	6	2489	50	4567	12496	43	1702	7	6	710	1	16	1	1	10037	10000	388	13	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	3	3	1	10458	86	2196	1	2208	233	5	0	800	10025	2159	231	202	30	53	30204	10194	10087	10000	10100	10000	10000	543890	468848	80469	10021	10040	10040	7424	3	7498	30440	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12479	25	1368	1682	0	1674	10831	1494	6	2480	50	4543	12496	44	742	7	3	710	1	16	1	1	10037	10000	316	2	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	0	0	0	10251	81	2203	1	2216	107	11	1	212	10025	2165	249	220	38	25	30175	10100	10113	10000	10100	10000	10000	543950	468848	80521	10021	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12487	19	1497	1679	0	1671	10835	1518	3	2441	50	4589	12485	47	773	7	3	710	1	16	1	1	10037	10000	251	3	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	0	0	0	10470	72	2217	1	2208	29	6	0	212	10025	2165	246	250	31	25	30183	10100	10086	10000	10100	10000	10000	543959	468848	80572	10021	10040	10040	7424	3	7498	30100	200	10000	10000	204	20000	20000	10162	10040	1	1	10201	100	99	100	100	10000	10000	100	12483	22	1592	1663	0	1700	10820	1553	3	2473	50	4519	12494	50	740	7	0	710	1	16	1	1	10037	10000	443	9	10000	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	37	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20044	10040	76	2	2	0	10632	63	2225	1	1960	365	10	0	464	10025	2186	253	233	34	25	30542	10010	10203	10000	10010	10000	10000	542981	468848	80021	1	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12469	12	1645	1588	0	1586	10968	1517	1	2469	50	4600	12497	23	813	0	640	2	16	3	3	10037	10000	313	3	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	2	2	10560	56	2232	1	1944	9	9	0	464	10025	2193	217	207	52	25	30033	10010	10303	10000	10010	10000	10000	543385	468848	80663	0	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	12	1645	1555	4	1600	10902	1512	6	2469	50	4513	12497	33	726	4	640	3	16	3	3	10037	10000	371	9	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	2	10503	65	2225	1	1952	232	8	0	464	10025	2186	217	206	43	25	30773	10010	10541	10000	10010	10000	10000	543385	468848	81285	0	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12461	12	1574	1550	0	1576	10944	1494	0	2485	50	4525	12477	23	780	4	640	3	16	3	3	10037	10000	472	2	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	2	2	10617	79	2246	1	1968	265	6	0	464	10025	2185	204	228	31	25	30017	10010	10229	10000	10010	10000	10000	543393	468848	80705	0	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10163	1	1	10021	10	9	10	10	10000	10000	10	12477	9	1689	1469	0	1518	10990	1527	0	2461	50	4559	12496	31	748	1	640	3	16	3	3	10037	10092	224	3	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	1	0	0	10530	58	2232	1	1968	544	8	0	464	10025	2193	241	211	27	25	30035	10010	10228	10000	10010	10000	10000	543285	468848	80063	0	10016	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	12	1546	1554	0	1598	10910	1476	2	2469	50	4576	12486	28	725	4	640	3	16	3	2	10037	10000	272	3	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	2	10566	52	2232	1	1952	525	8	0	464	10025	2186	205	266	20	25	30251	10010	10179	10000	10010	10000	10000	543397	468848	80675	0	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12471	14	1643	1525	0	1580	10913	1495	2	2477	50	4589	12484	31	782	0	640	2	16	3	3	10037	10000	350	4	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	76	2	0	0	10509	74	2225	1	1960	660	7	0	464	10025	2179	233	199	25	25	30190	10010	10328	10000	10010	10000	10000	543353	468848	80489	1	10016	10167	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12461	14	1654	1585	0	1567	10950	1531	4	2477	50	4617	12491	25	760	0	640	2	16	3	3	10037	10000	257	4	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	2	2	10599	68	2232	1	1952	546	9	0	464	10025	2186	201	236	16	25	30366	10010	10213	10000	10010	10000	10000	543389	468848	81161	0	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12477	12	1700	1526	1	1577	10904	1507	0	2469	50	4471	12480	31	828	0	640	3	16	3	2	10037	10000	327	4	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	0	10725	60	2225	1	1952	91	9	2	464	10025	2186	263	194	33	25	30033	10010	10431	10000	10010	10000	10000	543405	468848	80447	1	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12469	12	1576	1577	0	1546	10933	1496	0	2477	50	4555	12486	30	708	0	640	3	16	3	3	10037	10000	245	3	1	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	2	0	0	10590	128	2232	1	1960	488	8	0	464	10025	2200	233	252	33	25	30245	10010	10213	10000	10010	10000	10000	543385	468848	80060	0	10016	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	12	1637	1540	0	1562	10926	1491	2	2469	50	4510	12496	29	810	4	640	2	16	3	3	10037	10000	299	2	1	10000	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  stp s0, s1, [x6], #0x10
  stp s0, s1, [x7], #0x10
  stp s0, s1, [x8], #0x10
  stp s0, s1, [x9], #0x10
  stp s0, s1, [x10], #0x10
  stp s0, s1, [x11], #0x10
  stp s0, s1, [x12], #0x10
  stp s0, s1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5016

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160224	40155	300	0	0	0	0	0	10212	27	2300	1	1488	3130	6	208	40072	2293	534	588	12	25	241726	80110	81289	80000	80112	80016	80008	400599	1845076	644117	2	40120	0	40089	40101	20042	0	6	20105	240140	200	80016	80016	200	160032	160032	40114	40139	1	1	80201	100	99	100	100	80000	80000	100	82482	0	1589	2461	6	2474	80050	1561	0	2490	510	4490	82504	41	759	0	1	1	1	5117	16	40158	80014	80000	80000	80100	40141	40124	40098	40122	40157
160204	40141	301	0	0	0	0	0	9975	62	2327	1	1496	2444	7	156	40118	2266	436	444	38	25	241747	80114	82942	80000	80112	80012	80008	400583	1842436	650457	2	40127	0	40114	40142	20053	0	6	20062	240131	200	80016	80016	200	160032	160032	40133	40157	1	1	80201	100	99	100	100	80000	80000	100	82486	0	1300	2447	5	2501	80008	1534	0	2504	510	4571	82535	40	923	0	1	1	1	5117	16	40118	80014	80000	80000	80100	40114	40137	40164	40133	40176
160204	40142	300	0	0	0	0	0	9993	34	2325	1	1488	1389	5	236	40082	2257	648	367	32	25	241693	80110	81153	80000	80112	80016	80008	400599	1845287	646686	2	40078	0	40115	40115	20009	0	6	20098	240140	200	80016	80016	200	160032	160032	40143	40128	1	1	80201	100	99	100	100	80000	80000	100	82468	0	2113	2424	1	2482	80051	1537	0	2480	976	4631	82524	25	1525	0	1	1	1	5117	16	40143	80010	80000	80000	80100	40086	40126	40139	40106	40138
160204	40168	300	0	0	0	0	0	10212	30	2342	1	1144	1089	6	160	40110	2259	371	324	39	25	241809	80114	83123	80000	80112	80012	80007	400583	1843607	649086	2	40139	0	40129	40086	20014	0	6	20091	240140	200	80016	80016	200	160032	160032	40122	40094	1	1	80201	100	99	100	100	80000	80000	100	82494	0	1696	2476	3	2474	80024	1524	0	2474	976	4592	82522	24	1823	0	1	1	1	5117	16	40109	80014	80000	80000	80100	40135	40142	40156	40136	40109
160204	40110	301	0	0	0	0	0	10263	62	2295	1	1496	2973	6	228	40097	2247	479	586	41	25	242945	80110	82979	80000	80116	80016	80008	400599	1843991	648693	2	40118	0	40087	40154	20066	0	6	20062	240130	200	80016	80016	200	160032	160032	40122	40130	1	1	80201	100	99	100	100	80000	80000	100	82469	3	1384	2471	7	2454	80044	1500	0	2484	976	4687	82485	31	1543	0	1	1	1	5117	16	40143	80010	80000	80000	80100	40131	40132	40131	40149	40144
160204	40176	300	1	0	0	0	0	10041	21	2288	1	1472	2894	3	156	40103	2334	438	772	63	25	241356	80110	81248	80000	80116	80012	80008	400583	1842791	650984	2	40084	0	40102	40154	20063	0	6	20060	240131	200	80016	80016	200	160032	160032	40123	40113	1	1	80201	100	99	100	100	80000	80000	100	82472	0	1595	2463	4	2477	80039	1535	0	2494	976	4528	82527	16	1850	0	1	1	1	5117	16	40156	80010	80000	80000	80100	40127	40101	40120	40117	40186
160204	40154	300	0	0	0	0	0	9876	32	2327	1	1160	1467	5	200	40135	2266	513	617	47	25	241395	80110	82968	80000	80116	80016	80007	400583	1844135	650993	2	40074	0	40111	40158	20063	0	6	20094	240131	200	80016	80016	200	160032	160032	40119	40151	1	1	80201	100	99	100	100	80000	80000	100	82486	0	1328	2435	12	2449	80030	1508	0	2504	954	4619	82512	19	1556	0	1	1	1	5117	16	40105	80010	80000	80000	80100	40106	40102	40102	40156	40133
160204	40107	301	0	0	0	0	0	10215	35	2307	1	1504	3151	6	104	40119	2261	323	403	47	25	242476	80110	81825	80000	80112	80012	80007	400583	1844087	647568	2	40135	0	40100	40166	20074	0	6	20092	240140	200	80016	80016	200	160032	160032	40146	40124	1	1	80201	100	99	100	100	80000	80000	100	82468	4	1691	2462	12	2453	80024	1506	0	2476	510	4648	82511	27	1481	0	1	1	1	5117	16	40133	80014	80000	80000	80100	40153	40134	40139	40128	40126
160204	40131	301	0	0	0	0	0	9966	37	2339	1	1504	1524	4	264	40101	2305	684	257	44	25	242998	80110	81505	80000	80112	80012	80007	400583	1843962	646188	2	40069	0	40174	40113	20044	0	6	20036	240130	200	80016	80016	200	160032	160032	40134	40110	1	1	80201	100	99	100	100	80000	80000	100	82488	0	1611	2462	4	2483	80026	1520	0	2476	510	4666	82508	27	1883	0	1	1	1	5117	16	40110	80014	80000	80000	80100	40142	40126	40155	40126	40179
160204	40119	301	0	0	0	0	0	10245	40	2295	1	1504	1501	4	228	40105	2306	585	500	50	25	241704	80110	81536	80000	80112	80012	80006	400599	1841735	644374	2	40066	0	40144	40100	20011	0	6	20101	240140	200	80016	80016	200	160032	160032	40143	40179	1	1	80201	100	99	100	100	80000	80000	100	82496	0	1873	2449	3	2480	80034	1521	0	2488	510	4599	82523	38	1258	0	1	1	1	5117	16	40135	80010	80000	80000	80100	40197	40173	40119	40130	40110

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5025

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160044	40123	300	0	0	0	10032	60	2317	2	1256	2300	5	480	40153	2270	578	588	48	25	241736	80012	80640	80000	80010	80000	80000	400081	1846480	649587	2	40264	40176	40155	20098	3	20182	240010	20	80000	80000	20	160000	160000	40169	40264	1	1	80021	10	9	10	10	80000	80000	10	82504	2	2245	2447	0	2468	80091	1517	1	2502	516	4651	82565	62	1059	0	5020	0	3	0	7	16	0	4	4	40205	80002	80000	80000	80010	40235	40117	40159	40116	40211
160024	40200	301	1	0	0	9876	118	2377	2	1296	2138	14	492	40409	2258	620	657	164	25	243710	80244	81804	80000	80242	80000	80000	400081	1860340	652092	2	40140	40191	40230	20117	25	20196	240010	20	80240	80000	20	160000	160276	40288	40486	1	1	80021	10	9	10	10	80000	80000	10	82472	4	1323	2444	10	2485	80066	1512	0	2486	490	4782	82582	88	1438	0	5020	0	0	0	7	16	0	6	6	40268	80002	80000	80000	80010	40215	40174	40228	40110	40155
160024	40251	301	1	0	0	10155	111	2341	2	1264	2828	8	256	40226	2307	741	854	37	25	243953	80012	80798	80000	80010	80000	80000	400081	1844944	647772	2	40197	40180	40173	20188	3	20147	240010	20	80000	80000	20	160000	160000	40216	40146	1	1	80021	10	9	10	10	80000	80000	10	82470	4	1589	2444	2	2506	80070	1512	0	2476	588	4675	82579	122	1318	0	5020	0	0	0	4	16	0	5	5	40180	80002	80000	80000	80010	40140	40141	40209	40166	40184
160024	40202	301	1	1	0	10245	214	2368	2	1248	2974	7	464	40169	2272	910	486	36	25	241400	80012	81426	80000	80010	80000	80000	400081	1846048	647256	2	40208	40194	40190	20118	3	20211	240010	20	80000	80000	20	160000	160000	40180	40130	1	1	80021	10	9	10	10	80000	80000	10	82489	2	1445	2476	0	2484	80057	1528	0	2485	564	4628	82548	84	1741	1	5020	0	0	0	6	16	0	4	5	40134	80002	80000	80000	80010	40190	40264	40177	40235	40292
160024	40182	301	1	1	0	9987	122	2273	2	1248	1426	2	476	40260	2296	646	700	29	25	243282	80012	83133	80000	80010	80000	80000	400081	1847488	642746	2	40175	40184	40203	20131	46	20252	240010	20	80000	80000	20	160000	160000	40155	40384	1	1	80021	10	9	10	10	80000	80000	10	82498	2	1666	2454	0	2477	80089	1518	0	2480	496	4683	82559	75	1385	1	5020	0	0	0	4	16	0	6	4	40207	80002	80000	80000	80010	40138	40136	40203	40141	40224
160024	40173	301	1	0	0	9984	128	2358	2	1480	1232	8	420	40114	2271	749	425	72	25	242828	80012	81332	80000	80010	80000	80000	400661	1844032	647968	2	40132	40208	40209	20217	3	20181	240010	20	80000	80000	20	160000	160000	40202	40149	1	1	80021	10	9	10	10	80000	80000	10	82473	2	1771	2396	7	2500	80106	1531	0	2502	490	4789	82568	99	1041	1	5020	0	0	0	4	15	0	4	4	40199	80002	80000	80000	80010	40128	40162	40173	40145	40158
160024	40137	301	1	0	1	9954	184	2296	2	1296	3022	12	608	40235	2283	636	718	16	25	241145	80012	83348	80000	80010	80000	80000	400081	1848688	644718	2	40143	40186	40210	20245	3	20112	240010	20	80000	80000	20	160000	160000	40204	40174	1	1	80021	10	9	10	10	80000	80000	10	82487	2	1640	2490	12	2463	80069	1519	1	2468	718	4725	82570	107	1816	2	5020	0	0	0	4	16	0	6	5	40154	80002	80000	80000	80010	40216	40181	40172	40194	40152
160024	40276	301	1	1	1	10185	174	2299	3	1232	859	8	500	40297	2281	635	783	36	25	243318	80012	83176	80000	80010	80000	80000	400081	1845520	649584	2	40087	40228	40216	20111	3	20169	240010	20	80000	80000	20	160000	160000	40242	40206	1	1	80021	10	9	10	10	80000	80000	10	82468	2	1603	2409	19	2490	80140	1529	1	2467	558	4701	82533	85	1760	0	5020	0	0	0	3	16	0	5	5	40220	80002	80000	80000	80010	40165	40142	40200	40132	40164
160024	40138	301	1	1	0	9975	122	2293	2	1256	1800	7	352	40155	2292	750	440	19	25	241035	80012	83725	80000	80010	80000	80000	400081	1848208	643535	2	40112	40177	40216	20132	3	20207	240010	20	80000	80000	20	160000	160000	40358	40262	1	1	80021	10	9	10	10	80000	80000	10	82488	3	1849	2469	13	2477	80089	1505	0	2484	516	4730	82580	71	1264	0	5020	5	0	0	4	16	0	5	5	40169	80002	80000	80000	80010	40171	40200	40131	40094	40144
160024	40206	302	0	0	0	10317	233	2296	2	1272	1773	6	216	40138	2304	555	733	37	25	242668	80012	80298	80000	80010	80000	80000	400081	1844848	648682	2	40202	40105	40169	20144	3	20189	240010	20	80000	80000	20	160000	160000	40156	40141	1	1	80021	10	9	10	10	80000	80000	10	82475	0	1325	2447	10	2494	80110	1534	0	2484	992	4712	82559	113	1472	0	5020	0	0	0	5	16	0	4	4	40209	80002	80000	80000	80010	40254	40290	40214	40155	40174

STP (post-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations