Firestorm: STP (pre-index, D) measurements

Code:

  stp d0, d1, [x6, #0x10]!
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
9006	1166	8	1	1	1	6	10	0	1	0	11	0	1151	8	2	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	1	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1044	0	43	1	27	1004	3	0	14	26	10	1019	5	39	510	16	1163	1000	1	1	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	11	22	1	0	11	0	1151	20	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	36	1	14	1005	2	0	16	8	8	1019	0	35	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	0	8	16	1	0	5	0	1151	0	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	35	2	31	1003	0	0	22	16	3	1016	0	47	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	1	0	3	30	1	0	4	4	1151	16	16	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1016	0	35	2	18	1004	1	0	18	8	0	1020	4	43	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	6	16	1	0	14	0	1151	4	3	2	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	46	2	32	1005	1	0	22	10	11	1029	5	27	510	16	1163	1000	2	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	12	10	32	1	0	10	0	1151	6	5	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1016	0	44	3	16	1005	0	0	16	16	7	1036	4	35	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	6	7	16	1	0	9	0	1151	12	0	3	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1018	0	40	3	29	1005	1	0	22	10	8	1032	5	39	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	6	5	0	1	0	11	4	1151	0	0	9	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1020	0	39	6	16	1005	0	2	16	18	14	1022	5	35	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	1	0	6	7	34	1	0	0	0	1151	0	0	6	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1036	0	39	5	16	1005	0	0	20	8	0	1034	0	35	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	0	9	36	1	0	15	12	1151	8	2	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	35	2	12	1003	1	0	12	0	3	1000	0	31	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167

Test 2: Latency 3->3

Code:

  stp d0, d1, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	37	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20224	10040	76	5	0	0	5	0	0	10398	80	2218	1	2216	134	14	2	212	10025	2165	227	235	36	25	30275	10100	10120	10000	10100	10000	10000	543907	468848	80190	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12481	65	1561	1630	3	1700	10853	1522	0	2481	50	4401	12480	26	898	0	0	710	0	0	1	16	1	1	10037	10000	332	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	5	0	5	0	0	0	10323	59	2204	1	2232	144	16	0	212	10025	2165	249	212	51	25	30235	10100	10106	10000	10100	10000	10000	543881	468848	80263	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12489	30	1650	1646	0	1718	10828	1519	4	2481	50	4402	12482	34	782	0	0	710	0	0	1	16	1	1	10037	10000	380	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	0	4	4	0	0	10476	53	2211	1	2224	87	13	0	212	10025	2172	268	234	32	25	30232	10100	10079	10000	10100	10000	10000	543561	468848	80683	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12481	38	1638	1685	0	1695	10835	1526	8	2497	50	4486	12495	30	817	0	8	710	0	0	1	16	1	1	10037	10000	325	3	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	0	0	4	0	0	10497	76	2204	1	2216	70	15	0	1960	10025	2179	262	218	47	25	30192	10100	10091	10000	10100	10000	10000	543923	468848	80640	1	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	30	1481	1643	0	1668	10832	1510	0	2481	50	4405	12498	38	812	0	4	731	0	0	1	16	1	1	10037	10000	340	3	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	4	4	0	0	0	10335	101	2197	1	2216	138	13	0	212	10025	2151	200	226	29	25	30174	10100	10102	10000	10100	10115	10000	543379	473273	80340	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12497	35	1346	1632	0	1712	10818	1507	0	2481	50	4400	12479	35	758	7	0	710	0	0	1	16	1	1	10037	10000	373	4	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	0	4	0	0	0	10287	73	2218	1	2232	146	19	0	212	10025	2165	269	219	34	25	30267	10100	10148	10000	10100	10000	10000	543966	468848	80248	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12489	27	1513	1630	0	1706	10849	1527	0	2505	50	4409	12468	24	880	0	12	710	0	0	1	16	1	1	10037	10000	325	15	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	6	6	6	0	0	0	10473	72	2218	1	2224	127	13	0	212	10025	2179	208	234	41	25	30204	10100	10116	10000	10100	10000	10000	543904	468848	80389	1	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12497	49	1544	1634	0	1688	10829	1525	6	2473	50	4439	12470	28	748	0	0	710	0	0	1	16	1	1	10037	10000	240	3	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	76	5	0	5	0	0	0	10473	80	2218	1	2240	77	16	0	212	10025	2179	230	231	35	25	30181	10100	10160	10000	10100	10000	10000	543974	468848	80247	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12502	32	1560	1642	0	1703	10825	1499	0	2505	50	4442	12489	31	739	0	10	710	0	0	1	16	1	1	10037	10000	427	5	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	4	0	0	0	0	10374	72	2204	1	2216	106	18	0	212	10025	2165	254	219	26	25	30215	10100	10102	10000	10100	10000	10000	543930	468848	80280	0	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12472	35	1467	1653	0	1683	10830	1511	4	2489	50	4422	12482	26	773	0	0	710	0	0	1	16	1	1	10037	10000	276	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	4	4	0	4	0	0	10410	65	2211	1	2224	74	21	0	212	10025	2158	227	224	49	25	30231	10100	10094	10000	10100	10000	10000	543951	468848	80258	1	0	10022	10040	10040	7424	3	7498	30100	200	10000	10000	200	20238	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12501	27	1562	1665	0	1683	10841	1494	0	2473	50	4356	12480	32	729	0	4	710	0	0	1	16	1	1	10037	10000	270	6	10000	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	20	22	29	37	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20044	10040	75	10245	107	2263	2	1664	23	3	0	652	10025	2263	0	417	390	51	25	30445	10010	10323	10000	10010	10000	10000	543289	468848	80081	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12494	0	1966	1560	0	1601	10929	1534	2458	100	4404	12538	57	1126	640	0	0	3	16	3	3	10037	10000	364	4	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10107	96	2248	2	1728	281	4	0	820	10025	2242	0	402	422	49	25	30430	10010	10639	10000	10010	10000	10000	543377	468848	81539	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12494	0	2105	1570	0	1604	10906	1514	2470	100	4473	12518	54	1123	640	0	0	3	16	2	2	10037	10000	424	9	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10266	115	2253	2	1648	428	3	0	644	10025	2199	3	395	422	49	25	30439	10010	10326	10000	10010	10000	10000	543345	468848	81915	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12450	0	1954	1553	0	1608	10957	1540	2478	100	4427	12506	55	1207	640	0	0	3	16	3	3	10037	10000	240	8	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10320	102	2246	2	1720	279	4	0	688	10025	2236	0	380	415	76	25	30656	10010	10249	10000	10010	10000	10000	543321	468848	81600	0	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12462	0	2069	1548	0	1615	10926	1509	2470	100	4434	12515	55	1223	640	0	0	3	16	2	3	10037	10000	350	7	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10122	94	2284	2	1696	542	2	0	688	10025	2236	0	396	356	46	25	30238	10010	10029	10000	10010	10000	10000	543337	468848	80878	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	2	1	10021	10	9	10	10	10000	10000	10	12470	0	2035	1566	0	1548	10953	1515	2478	100	4404	12517	63	1166	640	0	0	2	16	2	3	10037	10000	247	2	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10140	121	2275	2	1544	542	3	0	820	10025	2232	0	458	390	39	25	30294	10010	10656	10000	10010	10000	10000	543337	468848	80108	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12458	0	2045	1584	0	1613	10942	1529	2450	100	4405	12525	63	1171	640	0	0	2	16	3	3	10037	10000	220	6	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	9930	107	2260	2	1704	174	1	0	656	10025	2208	0	428	366	60	25	30256	10010	10349	10000	10010	10000	10000	543225	468848	81036	1	0	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12454	0	2048	1586	0	1590	10931	1510	2470	100	4403	12529	56	1193	640	0	0	3	16	2	2	10037	10000	265	3	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10044	114	2239	2	1680	212	5	0	744	10025	2235	0	336	373	64	25	30281	10010	10163	10000	10010	10000	10000	543369	468848	80716	1	0	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12474	0	2003	1565	0	1585	10939	1508	2458	100	4507	12526	54	1137	640	0	0	3	16	3	3	10037	10000	412	4	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10305	85	2252	2	1720	215	3	0	636	10025	2249	0	413	372	62	25	30332	10010	10540	10000	10010	10000	10000	543313	468848	80573	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20240	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12454	0	1937	1605	0	1574	10935	1497	2470	100	4383	12530	56	1129	640	0	0	2	16	3	3	10037	10000	391	6	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	10209	92	2291	2	1688	23	0	0	700	10025	2228	0	443	415	56	25	30274	10010	10545	10000	10010	10000	10000	543193	468848	81187	1	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12466	0	2037	1610	0	1623	10921	1520	2466	100	4385	12529	47	1205	640	0	0	3	16	2	3	10037	10000	285	3	10000	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  stp d0, d1, [x6, #0x10]!
  stp d0, d1, [x7, #0x10]!
  stp d0, d1, [x8, #0x10]!
  stp d0, d1, [x9, #0x10]!
  stp d0, d1, [x10, #0x10]!
  stp d0, d1, [x11, #0x10]!
  stp d0, d1, [x12, #0x10]!
  stp d0, d1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	24	29	37	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160224	40264	301	3	3	0	0	0	0	10188	131	2257	1	0	1688	864	15	0	228	40173	2230	700	904	74	25	243203	80102	82584	80000	80100	80000	80000	400531	1850800	644311	0	2	40175	40322	40223	20239	3	20222	240100	200	80000	80000	200	160000	160000	40233	40359	1	1	80201	100	99	100	100	80000	80000	100	82500	50	2310	2376	18	2442	80116	1502	0	2468	254	4793	82560	133	1984	0	0	0	0	5110	1	16	1	1	40276	80002	80000	80000	80100	40238	40158	40205	40257	40317
160204	40327	302	6	0	6	0	0	0	10128	171	2239	1	0	1976	1817	11	0	516	40191	2237	713	643	85	25	243016	80102	83841	80000	80100	80000	80000	400531	1849792	648707	1	2	40195	40234	40240	20177	3	20150	240100	200	80000	80136	200	160000	160000	40203	40192	1	1	80201	100	99	100	100	80000	80000	100	82484	30	2275	2417	7	2423	80114	1522	10	2492	254	4718	82558	142	2855	0	0	0	0	5110	1	16	1	1	40194	80002	80000	80000	80100	40230	40144	40231	40210	40248
160204	40252	301	5	0	5	0	0	0	10107	169	2225	1	0	1936	2019	15	0	264	40223	2177	932	687	71	25	242744	80102	82804	80000	80100	80000	80000	400531	1852480	648850	1	2	40298	40287	40231	20178	3	20177	240100	200	80000	80000	200	160000	160000	40222	40213	1	1	80201	100	99	100	100	80000	80000	100	82500	35	2734	2371	5	2433	80177	1511	5	2476	254	4754	82539	92	2596	0	10	0	0	5110	1	16	1	1	40292	80002	80000	80000	80100	40239	40211	40245	40218	40236
160204	40194	302	5	0	5	0	0	0	10068	155	2246	1	0	1960	3493	15	0	264	40203	2212	656	681	65	25	242735	80102	83610	80000	80100	80000	80000	400531	1852384	651655	1	2	40260	40317	40196	20140	3	20199	240100	200	80000	80000	200	160000	160000	40201	40269	1	1	80201	100	99	100	100	80000	80000	100	82468	14	1472	2380	13	2447	80123	1513	0	2476	510	4733	82561	93	1680	0	0	0	0	5110	1	16	1	1	40251	80002	80000	80000	80100	40193	40205	40216	40190	40265
160204	40177	302	3	0	0	0	0	0	9840	112	2271	1	0	1704	2628	12	0	284	40167	2244	615	718	63	25	243552	80102	81187	80000	80100	80000	80000	400531	1849648	648702	1	2	40224	40217	40247	20154	3	20142	240100	200	80000	80000	200	160000	160000	40261	40199	1	1	80201	100	99	100	100	80000	80000	100	82502	20	1454	2424	10	2448	80114	1472	0	2472	510	4698	82558	137	2017	0	3	0	0	5110	1	16	1	1	40291	80002	80000	80000	80100	40253	40207	40237	40272	40335
160204	40207	301	4	4	4	0	0	0	10095	201	2250	1	0	1704	3096	13	0	264	40225	2211	915	753	83	25	243140	80102	83003	80000	80100	80000	80000	400531	1847680	649089	0	2	40223	40236	40202	20187	3	20199	240100	200	80000	80000	200	160000	160000	40189	40309	1	1	80201	100	99	100	100	80000	80000	100	82476	24	1767	2381	2	2480	80138	1502	0	2472	358	4684	82537	90	1982	13	0	0	0	5110	1	16	1	1	40268	80002	80000	80000	80100	40242	40282	40150	40268	40170
160204	40294	302	4	0	4	4	0	0	10032	143	2271	1	0	1704	823	15	0	264	40243	2237	559	574	70	25	243909	80102	81194	80000	80100	80000	80000	400531	1852000	643840	1	2	40213	40289	40227	20182	3	20259	240100	200	80000	80000	200	160000	160000	40217	40201	1	1	80201	100	99	100	100	80000	80000	100	82504	22	2005	2369	15	2467	80168	1508	0	2484	510	4812	82556	105	2649	0	0	0	0	5110	1	16	1	1	40190	80002	80000	80000	80100	40169	40200	40322	40204	40325
160204	40310	302	4	0	4	4	0	0	10026	179	2278	1	0	1712	782	13	0	276	40210	2237	683	692	79	25	241528	80102	83596	80000	80100	80000	80000	400531	1847248	650266	0	2	40187	40274	40267	20213	3	20183	240100	200	80000	80000	200	160000	160000	40261	40255	1	1	80201	100	99	100	100	80000	80000	100	82504	22	2254	2420	4	2496	80105	1509	0	2480	510	4657	82553	82	1502	0	0	0	0	5110	1	17	1	1	40229	80002	80000	80000	80100	40196	40234	40313	40192	40238
160204	40229	301	4	4	4	4	0	0	10107	163	2264	1	0	1672	1440	17	0	264	40250	2216	800	834	39	25	243259	80102	81477	80000	80100	80000	80000	400531	1851064	648658	1	2	40301	40248	40371	20152	3	20213	240100	200	80000	80000	200	160000	160000	40229	40238	1	1	80201	100	99	100	100	80000	80000	100	82471	21	2321	2423	3	2461	80112	1504	0	2472	486	4668	82530	97	2100	0	3	0	0	5110	1	16	1	1	40229	80002	80000	80000	80100	40214	40264	40301	40265	40217
160204	40263	302	4	0	0	4	0	0	10119	148	2271	1	0	1672	1274	11	0	276	40274	2230	987	936	76	25	241731	80102	83589	80000	80100	80000	80000	400531	1845400	645810	0	2	40278	40179	40322	20221	3	20247	240100	200	80000	80000	200	160000	160000	40210	40223	1	1	80201	100	99	100	100	80000	80000	100	82488	30	2263	2412	12	2474	80136	1516	4	2484	510	4776	82557	95	2014	0	0	0	0	5110	1	16	1	1	40197	80002	80000	80000	80100	40158	40298	40210	40221	40235

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	24	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160044	40186	301	0	2	2	0	0	0	0	10332	40	2239	3	0	1960	115	4	264	40149	2205	659	920	42	25	243619	80012	80229	80000	80010	80000	80000	400081	1843096	649429	1	2	40113	0	40188	40217	20116	0	3	20123	240010	20	80000	80000	20	160000	160000	40137	40159	1	1	80021	10	9	10	10	80000	80000	10	82503	20	1224	2436	18	2450	80053	1522	3	2492	254	4631	82486	42	1591	14	0	0	5020	14	16	9	7	40174	80002	80000	80000	80010	40200	40144	40167	40170	40202
160024	40162	301	0	3	0	0	3	0	0	10320	71	2218	1	0	1944	514	8	264	40141	2198	651	428	56	25	243505	80012	83470	80000	80010	80000	80000	400081	1843984	645865	1	2	40122	0	40192	40158	20113	0	3	20157	240010	20	80000	80000	20	160000	160000	40173	40215	1	1	80021	10	9	10	10	80000	80000	10	82474	20	1766	2426	9	2465	80058	1526	0	2476	254	4654	82513	38	2099	14	3	0	5020	9	16	10	11	40150	80002	80000	80000	80010	40169	40144	40147	40181	40143
160024	40150	301	0	3	3	0	3	0	0	9969	83	2217	1	0	1416	1534	7	264	40157	2184	494	652	73	25	242702	80012	82523	80000	80010	80000	80000	400081	1844152	645495	1	2	40118	0	40174	40152	20150	0	3	20182	240010	20	80000	80000	20	160000	160000	40168	40178	1	1	80021	10	9	10	10	80000	80000	10	82474	20	1969	2429	3	2458	80044	1505	3	2484	254	4636	82510	53	1612	14	0	1	5020	9	16	7	9	40147	80002	80000	80000	80010	40180	40166	40147	40168	40122
160024	40162	301	0	2	0	0	0	0	0	10248	58	2272	1	0	1704	562	5	292	40146	2223	677	552	50	25	240535	80012	81839	80000	80010	80000	80000	400081	1845112	646755	1	2	40171	0	40139	40126	20062	0	3	20159	240010	20	80000	80000	20	160000	160000	40171	40133	1	1	80021	10	9	10	10	80000	80000	10	82486	16	1717	2464	2	2461	80046	1509	0	2492	508	4539	82529	42	1399	14	0	0	5020	9	16	9	14	40177	80002	80000	80000	80010	40195	40185	40159	40172	40131
160024	40319	301	0	2	0	0	0	0	0	10095	38	2261	1	0	1704	1479	9	460	40190	2238	596	472	50	25	240669	80012	83368	80000	80010	80130	80000	400081	1844272	643830	1	2	40094	0	40147	40138	20087	0	3	20156	240010	20	80000	80000	20	160000	160000	40158	40208	2	1	80021	10	9	10	10	80000	80000	10	82482	16	2067	2431	11	2470	80056	1506	0	2484	508	4596	82503	49	1620	14	0	0	5020	13	16	12	9	40183	80002	80000	80000	80010	40151	40118	40178	40173	40188
160024	40162	300	0	2	0	0	0	0	0	10029	76	2305	1	0	1680	151	6	480	40108	2240	541	451	81	25	242906	80012	83609	80000	80010	80000	80000	400081	1846936	647746	1	2	40118	0	40189	40170	20136	0	3	20108	240010	20	80000	80000	20	160000	160000	40160	40145	1	1	80021	10	9	10	10	80000	80000	10	82490	16	1689	2441	7	2466	80044	1527	2	2472	510	4626	82497	39	1753	14	0	0	5020	10	16	9	7	40159	80002	80000	80000	80010	40151	40188	40133	40190	40171
160024	40191	300	0	2	2	0	0	0	0	10179	50	2274	1	0	1688	3591	5	472	40112	2232	358	536	52	25	243201	80012	83271	80000	80010	80000	80000	400081	1847416	648678	1	2	40110	0	40161	40160	20094	0	3	20121	240010	20	80000	80000	20	160000	160000	40134	40233	1	1	80021	10	9	10	10	80000	80000	10	82474	16	1707	2431	16	2463	80058	1506	0	2464	510	4553	82506	45	1606	14	0	0	5020	9	16	9	12	40176	80002	80000	80000	80010	40125	40147	40121	40143	40202
160024	40173	300	0	2	2	0	0	0	0	10077	62	2273	1	0	1616	188	6	420	40158	2233	469	548	46	25	243091	80012	83127	80000	80010	80000	80000	400081	1843240	642193	1	2	40171	0	40143	40165	20125	0	3	20153	240010	20	80000	80000	20	160000	160000	40137	40144	1	1	80021	10	9	10	10	80000	80000	10	82502	18	2216	2453	3	2472	80070	1530	2	2480	508	4540	82490	48	1327	14	2	0	5020	9	16	9	7	40162	80002	80000	80000	80010	40149	40144	40166	40194	40125
160024	40134	301	0	2	2	0	2	0	0	10017	59	2304	1	0	1656	840	7	292	40117	2232	603	660	59	25	243761	80012	84888	80000	80010	80000	80000	400081	1845136	649913	1	2	40135	0	40184	40134	20081	0	3	20124	240010	20	80000	80000	20	160000	160000	40137	40145	1	1	80021	10	9	10	10	80000	80000	10	82497	18	2297	2451	17	2465	80085	1514	0	2479	510	4648	82519	49	1849	14	4	0	5020	8	16	9	7	40350	80002	80000	80000	80010	40126	40158	40180	40151	40156
160024	40174	301	0	2	2	0	0	0	0	9942	62	2287	1	0	1496	2949	5	248	40121	2252	446	554	70	25	240281	80012	80085	80000	80010	80000	80000	400081	1844992	641001	1	2	40120	0	40141	40140	20100	0	3	20120	240010	20	80000	80000	20	160000	160000	40125	40135	1	1	80021	10	9	10	10	80000	80000	10	82510	16	1540	2421	6	2469	80056	1517	0	2496	510	4569	82492	44	1533	14	2	0	5020	8	16	11	12	40125	80002	80000	80000	80010	40162	40158	40149	40183	40175

STP (pre-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations