Firestorm: STP (pre-index, Q) measurements

Code:

  stp q0, q1, [x6, #0x10]!
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
9005	1165	8	1	0	0	0	14	16	1	0	12	0	1150	18	3	3	25	3000	1000	2000	1000	2000	5999	12535	1	1140	1165	1165	3	24	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2029	12	93	7	24	2012	0	1	33	0	15	2014	12	77	12	1	515	8	16	6	6	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	1	1	0	15	43	1	0	17	12	1150	7	0	3	25	3000	1000	2000	1000	2000	5999	12492	1	1140	1165	1165	3	25	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2035	14	111	5	28	2012	0	1	17	20	12	2017	12	93	12	0	516	5	16	5	6	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	0	1	6	14	19	2	0	10	0	1150	10	11	2	25	3000	1000	2000	1000	2000	5999	12493	1	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2044	13	61	4	16	2013	0	1	31	8	12	2018	12	53	12	1	516	7	16	6	6	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	0	2	0	15	0	1	0	18	12	1150	0	0	3	25	3000	1000	2000	1000	2000	5999	12465	0	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2029	12	53	5	24	2013	1	2	31	8	18	2031	12	45	12	1	516	6	16	6	5	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	1	1	0	14	35	1	0	7	0	1150	12	4	30	25	3000	1000	2000	1000	2000	5999	12477	1	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2027	13	93	6	23	2012	0	0	0	0	15	2000	12	61	12	0	516	7	16	6	6	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	8	1	1	1	6	15	43	1	0	11	4	1150	7	8	0	25	3000	1000	2000	1000	2000	5999	12418	0	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2031	14	69	6	24	2012	1	2	18	8	12	2031	12	85	12	2	516	6	16	5	4	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	8	1	1	1	0	14	0	2	0	16	0	1150	11	0	3	25	3000	1000	2000	1000	2000	5999	12542	0	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2045	13	69	3	15	2012	0	0	23	10	18	2018	12	61	12	1	515	7	16	7	7	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	1	0	0	16	24	1	0	12	12	1150	0	16	5	25	3000	1000	2000	1000	2000	5999	12480	1	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2037	13	61	4	20	2012	0	1	17	14	12	2015	12	93	12	1	516	6	16	6	7	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	0	1	0	15	12	2	0	15	12	1150	8	10	3	25	3000	1000	2000	1000	2000	5999	12588	1	1140	1165	1165	3	23	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2029	12	77	2	45	2012	1	0	31	14	12	2043	12	88	12	1	516	6	16	6	6	1162	1000	2000	1000	1166	1166	1166	1166	1166
9004	1165	9	1	1	1	0	18	37	1	0	18	12	1150	8	3	8	25	3000	1000	2000	1000	2000	5999	12501	0	1140	1165	1165	3	24	3000	2000	4000	1165	1165	1	1	8001	1000	1000	2046	12	93	7	21	2012	0	1	35	14	12	2031	12	53	12	2	516	6	16	7	6	1162	1000	2000	1000	1166	1166	1166	1166	1166

Test 2: Latency 3->3

Code:

  stp q0, q1, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1656

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20223	10273	77	4	4	4	10677	73	2194	1	2200	9	0	212	11733	2172	1	230	295	256	25	30100	10100	20000	10100	20000	76272	468188	1	10219	10273	10316	7739	3	9175	30100	200	20000	200	40000	11684	11718	1	1	10201	100	99	100	100	10000	10000	100	22477	34	1341	2366	48	2429	20125	1490	0	2479	50	4609	22523	66	1212	14	4	710	1	16	1	1	10300	10000	118	0	0	20000	10100	11666	11713	11690	11687	11709
20204	10271	77	3	0	3	10641	73	2203	1	2208	11	0	212	10249	2163	1	233	318	146	25	30100	10100	20000	10100	20000	74205	538408	0	11647	11702	11692	9106	3	9100	30100	200	20000	200	40000	11706	11690	1	1	10201	100	99	100	100	10000	10000	100	22486	42	1881	1976	36	2016	20564	1513	0	2472	50	4662	22491	68	1385	14	8	710	1	16	1	1	11692	10000	124	1	2	20000	10100	10310	10256	10323	10288	10241
20204	10310	76	4	0	0	10470	77	2202	1	2216	12	0	212	10205	2177	2	222	310	209	25	30100	10100	20000	10100	20000	74181	539252	0	11673	11653	11724	9086	3	9201	30100	200	20000	200	40000	11722	11699	1	1	10201	100	99	100	100	10000	10000	100	22521	38	1265	2370	31	2413	20133	1514	4	2472	50	4611	22501	58	1280	14	4	710	1	16	1	1	10190	10000	57	2	1	20000	10100	10257	10374	10274	10226	10309
20204	10292	77	4	4	0	10617	81	2203	1	2208	8	0	212	11673	2151	2	271	275	205	25	30100	10100	20000	10100	20000	73806	538628	0	11664	11676	11699	9089	3	9179	30100	200	20000	200	40000	11732	11667	1	1	10201	100	99	100	100	10000	10000	100	22470	29	1683	1983	10	2002	20521	1472	6	2487	50	4632	22520	82	1263	14	3	710	1	16	1	1	11681	10000	124	1	0	20000	10100	11654	11678	11469	11689	11677
20204	11706	88	4	4	4	10728	72	2202	1	2216	12	0	212	11703	2172	0	319	336	186	25	30100	10100	20000	10100	20000	74047	538936	0	11666	11606	11704	9121	3	9115	30100	200	20000	200	40000	11739	11680	1	1	10201	100	99	100	100	10000	10000	100	22489	29	1469	2382	27	2424	20137	1494	0	2496	50	4698	22528	62	1299	14	3	710	1	16	1	1	10229	10000	58	2	1	20000	10100	10313	10227	10220	10320	10277
20204	10270	76	3	0	3	10704	75	2196	1	2216	7	0	752	11691	2150	1	272	295	166	25	30100	10100	20000	10100	20000	74082	537210	0	11676	11700	11661	9098	3	9136	30100	200	20000	200	40000	11682	11665	1	1	10201	100	99	100	100	10000	10000	100	22485	26	1544	1988	29	2007	20518	1485	0	2479	50	4617	22538	50	1225	14	3	710	1	16	1	1	11702	10000	143	3	0	20000	10100	10280	10275	10249	10287	10332
20204	10280	77	4	0	0	10620	80	2209	1	2224	15	0	212	11679	2172	0	361	226	216	25	30100	10100	20000	10100	20000	74061	538388	0	11705	11722	11683	9113	3	9180	30100	200	20000	200	40000	11705	11704	1	1	10201	100	99	100	100	10000	10000	100	22502	26	1533	1975	42	1980	20518	1540	0	2472	50	4637	22507	76	1441	14	3	727	1	16	1	1	11697	10000	143	4	1	20000	10100	10286	10270	10246	10281	10233
20204	10256	77	3	0	3	10755	65	2189	1	2208	11	0	212	10201	2171	0	265	219	136	25	30100	10100	20000	10100	20000	74150	539492	0	11685	11687	10255	7704	3	7703	30100	200	20000	200	40000	10226	10253	1	1	10201	100	99	100	100	10000	10000	100	22501	26	1346	2370	48	2429	20113	1553	0	2495	50	4626	22513	55	1247	14	3	710	1	16	1	1	10239	10000	38	3	6	20000	10100	11695	11695	11693	11687	11679
20204	11663	88	3	3	0	10500	77	2223	1	2208	4	0	212	11627	2218	0	244	299	187	25	30100	10100	20000	10100	20000	74106	540356	0	11644	11640	11536	9111	3	9166	30100	200	20000	200	40000	11524	11704	1	1	10201	100	99	100	100	10000	10000	100	22493	20	1528	1959	15	1992	20507	1492	4	2488	50	4624	22526	65	1308	14	2	710	1	16	1	1	11681	10000	140	1	2	20000	10100	11738	11699	11709	11673	11689
20204	11659	87	2	0	0	10710	76	2188	1	2200	6	0	212	11689	2165	2	250	242	167	25	30100	10100	20000	10100	20000	74091	537476	0	11657	11656	11696	9082	3	9162	30100	200	20000	200	40000	11659	11668	1	1	10201	100	99	100	100	10000	10000	100	22501	26	1566	2018	25	1999	20502	1493	3	2472	50	4602	22518	49	1316	14	0	710	1	16	1	1	11684	10000	125	1	3	20000	10100	11746	11710	11688	11675	11659

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0310

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20043	10297	85	2	1	0	1	2	10275	78	2268	1	1728	5	0	880	10178	2251	0	286	324	73	25	30010	10010	20000	10010	20000	75108	470248	1	11433	11412	10287	7671	3	8886	30010	20	20000	20	40000	11449	10259	1	1	10021	10	9	10	10	10000	10000	10	22498	6	1307	2392	49	2120	20114	1525	2	2489	50	4675	22548	38	1174	0	0	0	641	5	16	5	5	11361	10000	77	3	1	20000	10010	10207	11379	10209	11479	10205
20024	10210	85	0	1	0	1	0	10197	70	2260	1	1608	7	0	944	11339	2248	2	260	317	155	25	30010	10010	20000	10010	20000	74971	468856	1	11361	11423	10363	7660	3	7696	30010	20	20000	20	40000	10236	11415	1	1	10021	10	9	10	10	10000	10000	10	22469	0	1590	2381	30	2081	20094	1535	0	2481	50	4474	22525	41	966	0	0	0	641	5	16	5	5	10263	10000	82	2	0	20000	10010	10215	11425	10273	11430	10238
20024	10227	85	0	1	0	1	0	10158	78	2250	1	1712	6	0	724	11417	2241	1	231	303	133	25	30010	10010	20000	10010	20000	75083	468544	1	11463	11449	10290	7709	3	7727	30010	20	20000	20	40000	10247	11427	1	1	10021	10	9	10	10	10000	10000	10	22501	0	1630	2376	51	2008	20109	1503	0	2485	50	4585	22530	50	1220	0	0	0	641	5	16	5	4	10297	10000	68	2	0	20000	10010	11412	10241	11401	10249	11394
20024	11357	77	0	1	0	1	0	9819	82	2301	1	1720	3	1	712	11389	2257	2	291	267	143	25	30010	10010	20000	10010	20000	77529	523600	1	10223	10188	11344	8850	3	8873	30010	20	20000	20	40000	11415	10209	1	1	10021	10	9	10	10	10000	10000	10	22458	8	1315	1983	55	2416	20438	1505	0	2477	50	4622	22523	52	1173	0	0	0	641	5	16	5	4	11429	10000	84	2	2	20000	10010	10223	11433	10221	11413	10248
20024	10245	85	1	1	1	1	0	10104	79	2277	1	1712	5	0	932	10217	2245	1	296	268	119	25	30010	10010	20000	10010	20000	78153	527248	1	10228	10206	11432	8891	3	8897	30010	20	20000	20	40000	11376	10291	1	1	10021	10	9	10	10	10000	10000	10	22481	4	1124	2044	60	2401	20461	1505	1	2497	50	4726	22535	40	1198	0	0	0	641	5	16	4	5	11432	10000	49	4	0	20000	10010	10277	11409	10245	11418	10186
20024	10203	86	0	1	0	1	0	10266	78	2305	1	1632	4	0	704	10208	2211	0	255	240	105	25	30010	10010	20000	10010	20000	77870	524368	1	10188	10264	11405	8887	3	8861	30010	20	20000	20	40000	11365	10250	1	1	10021	10	9	10	10	10000	10000	10	22473	8	1214	2084	47	2442	20431	1526	0	2465	50	4593	22508	49	1114	0	0	0	641	5	16	5	4	11486	10000	79	4	0	20000	10010	11426	10250	11413	10184	11396
20024	11401	76	0	1	0	1	0	10095	82	2270	1	1504	6	0	724	11390	2215	0	249	260	156	25	30010	10178	20000	10010	20000	77637	528688	1	10194	10224	11443	8842	3	8827	30010	20	20000	20	40000	11427	10309	1	1	10021	10	9	10	10	10000	10000	10	22467	9	1251	2069	48	2378	20411	1487	0	2469	50	4580	22512	60	1324	0	0	0	641	3	16	4	4	11423	10000	68	1	0	20000	10010	10288	11401	10321	11425	10233
20024	10180	77	0	1	0	1	0	10077	84	2277	1	1712	5	0	724	10253	2222	1	237	318	132	25	30010	10010	20000	10010	20000	77349	526528	1	10231	10231	11453	8854	3	8859	30010	20	20000	20	40000	11357	10208	1	1	10021	10	9	10	10	10000	10000	10	22489	12	1186	2063	43	2450	20441	1504	1	2481	50	4641	22533	37	1133	0	0	0	641	4	16	4	5	11366	10000	49	0	0	20000	10010	10285	11383	10241	11401	10295
20024	10222	85	1	1	0	1	1	10338	46	2291	1	1632	3	0	948	10200	2247	1	280	272	157	25	30010	10010	20000	10010	20000	77841	525760	1	10225	10237	11392	8853	3	8857	30010	20	20000	20	40000	10243	11446	1	1	10021	10	9	10	10	10000	10000	10	22477	0	1118	2100	46	2393	20459	1497	0	2485	50	5049	22531	52	993	0	0	0	641	5	16	4	4	11398	10000	53	0	0	20000	10010	10259	11371	10269	11393	10274
20024	10256	85	0	1	0	1	0	10266	65	2305	1	1704	4	0	724	11372	2234	0	285	306	158	25	30010	10010	20000	10010	20000	75103	468184	1	11396	11482	10252	7713	3	7692	30010	20	20000	20	40000	10228	11372	1	1	10021	10	9	10	10	10000	10000	10	22478	10	1537	2376	35	2147	20108	1492	0	2485	50	4684	22515	50	1170	0	0	0	641	4	16	4	5	10205	10000	45	2	0	20000	10010	11409	10291	11403	10194	11481

Test 3: throughput

Count: 8

Code:

  stp q0, q1, [x6, #0x10]!
  stp q0, q1, [x7, #0x10]!
  stp q0, q1, [x8, #0x10]!
  stp q0, q1, [x9, #0x10]!
  stp q0, q1, [x10, #0x10]!
  stp q0, q1, [x11, #0x10]!
  stp q0, q1, [x12, #0x10]!
  stp q0, q1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0026

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160223	80227	600	4	0	0	0	0	9762	96	2326	1	1408	11	100	80126	2301	547	840	61	25	240104	80104	160000	80100	160000	400511	3685640	1	0	4	80140	80156	80148	60076	3	60156	240100	200	160000	200	320000	80151	80146	1	1	80201	100	99	100	100	80000	80000	100	162498	13	1060	2474	7	2490	160112	1515	2	2498	222	4694	162583	116	1057	0	0	0	0	5110	0	0	1	16	1	1	80161	80004	160000	80100	80168	80141	80193	80154	80200
160204	80201	601	3	0	0	0	0	9789	99	2327	1	1272	11	264	80148	2298	669	677	43	25	240104	80104	160000	80100	160000	400511	3686840	0	0	4	80150	80134	80132	60088	3	60138	240100	200	160000	200	320000	80130	80175	1	1	80201	100	99	100	100	80000	80000	100	162504	13	1626	2452	7	2484	160099	1518	0	2486	222	4613	162570	87	1302	0	2	0	0	5110	0	0	1	16	1	1	80194	80004	160000	80100	80149	80241	80153	80201	80179
160204	80145	601	3	0	3	0	0	9876	89	2337	1	1384	9	172	80133	2302	499	854	50	25	240104	80104	160000	80100	160000	400511	3685328	1	0	4	80112	80196	80152	60108	3	60109	240100	200	160000	200	320000	80123	80160	1	1	80201	100	99	100	100	80000	80000	100	162475	17	1653	2440	2	2492	160145	1539	0	2486	222	4645	162568	94	1563	0	0	0	0	5110	0	0	1	16	1	1	80164	80004	160000	80100	80174	80150	80212	80190	80210
160204	80143	601	3	0	0	0	0	9789	156	2310	1	1408	13	256	80120	2289	1020	1094	103	25	240104	80104	160000	80100	160000	400511	3686816	1	0	4	80139	80163	80182	60090	3	60099	240100	200	160000	200	320000	80135	80138	1	1	80201	100	99	100	100	80000	80000	100	162474	9	1539	2494	1	2476	160094	1501	0	2480	190	4676	162560	98	1281	0	6	0	0	5110	0	0	1	16	1	1	80170	80004	160000	80100	80168	80246	80173	80184	80189
160204	80119	601	4	4	4	0	0	9873	198	2318	1	1256	15	252	80199	2306	880	1015	104	25	240104	80104	160060	80100	160000	400511	3685136	0	0	4	80130	80161	80237	60072	3	60126	240100	200	160000	200	320000	80213	80175	1	1	80201	100	99	100	100	80000	80000	100	162490	29	1035	2461	1	2505	160142	1537	4	2502	226	4700	162573	124	2342	21	0	0	0	5110	0	0	1	16	1	1	80146	80004	160000	80100	80206	80183	80173	80169	80165
160204	80175	601	3	3	0	3	0	10053	148	2326	1	1216	12	100	80159	2293	968	884	64	25	240104	80104	160000	80100	160000	400511	3686648	1	0	4	80176	80183	80214	60186	3	60145	240100	200	160000	200	320000	80229	80138	1	1	80201	100	99	100	100	80000	80000	100	162492	17	1232	2470	9	2502	160063	1527	6	2498	222	4706	162578	91	1659	0	0	0	0	5110	0	0	1	16	1	1	80172	80004	160000	80100	80190	80160	80226	80240	80210
160204	80157	600	3	3	0	3	0	9765	186	2333	1	1288	18	272	80179	2289	707	754	52	25	240104	80104	160000	80100	160000	400511	3688160	1	0	4	80100	80118	80207	60101	3	60167	240100	200	160000	200	320000	80130	80266	1	1	80201	100	99	100	100	80000	80000	100	162500	32	1186	2445	3	2503	160119	1533	3	2490	212	4755	162560	98	1592	0	0	0	0	5110	0	0	1	16	1	1	80163	80004	160000	80100	80155	80238	80180	80160	80155
160204	80146	601	2	0	0	0	0	9786	82	2311	1	1256	14	100	80135	2296	571	980	52	25	240104	80104	160000	80100	160000	400511	3688880	1	0	4	80220	80207	80202	60072	3	60138	240100	200	160000	200	320000	80158	80145	1	1	80201	100	99	100	100	80000	80000	100	162500	20	1427	2450	1	2479	160096	1509	0	2504	282	4666	162589	78	1832	0	3	0	0	5110	0	0	1	16	1	1	80129	80004	160000	80100	80242	80137	80156	80184	80203
160204	80184	601	3	0	0	0	1	9675	157	2315	1	1264	16	104	80207	2279	734	952	48	25	240104	80104	160000	80100	160000	400511	3687464	1	0	4	80146	80194	80203	60142	3	60120	240100	200	160000	200	320000	80201	80223	1	1	80201	100	99	100	100	80000	80000	100	162500	23	1799	2465	5	2500	160109	1526	0	2490	178	4647	162556	92	1824	0	0	0	0	5110	0	0	1	16	1	1	80177	80004	160000	80100	80226	80129	80149	80234	80211
160204	80173	600	3	0	3	3	0	9792	167	2324	1	1240	13	220	80174	2311	618	546	87	25	240104	80104	160060	80100	160000	400511	3687728	1	0	4	80139	80179	80165	60128	3	60104	240100	200	160000	200	320000	80245	80176	1	1	80201	100	99	100	100	80000	80000	100	162499	17	2276	2436	2	2480	160123	1521	0	2482	158	4674	162584	112	1806	0	5	0	0	5110	0	0	1	16	1	1	80225	80004	160000	80100	80136	80164	80278	80270	80199

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0025

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160043	80199	600	4	0	0	0	0	0	0	9588	150	2357	1	0	0	1272	13	264	80240	2251	838	635	79	25	240014	80014	160000	80010	160000	400061	3688184	0	5	4	80324	80156	80175	60094	3	60181	240010	20	160000	20	320000	80142	80171	1	1	80021	10	9	10	10	80000	80000	10	162508	28	2501	2430	6	2501	160167	1499	0	2488	492	4726	162572	155	2275	0	4	5020	0	7	5	16	0	3	3	80226	80004	160000	80010	80123	80199	80202	80304	80123
160024	80134	601	3	0	0	0	3	0	0	9879	183	2297	1	0	0	1496	18	276	80169	2278	988	838	41	25	240014	80014	160000	80010	160000	400061	3681800	1	10	4	80244	80152	80197	60170	3	60230	240010	20	160000	20	320000	80257	80223	1	1	80021	10	9	10	10	80000	80000	10	162509	18	1786	2455	4	2496	160071	1512	3	2505	212	4743	162551	107	2872	0	6	5020	0	7	3	16	0	3	2	80080	80004	160000	80010	80187	80110	80145	80127	80139
160024	80100	600	1	1	0	0	1	0	0	9912	94	2347	1	0	0	1432	6	264	80068	2324	741	913	48	25	240014	80014	160000	80010	160000	400061	3682928	0	10	4	80112	80188	80220	60061	3	60127	240010	20	160000	20	320000	80195	80094	1	1	80021	10	9	10	10	80000	80000	10	162510	13	1352	2474	7	2504	160111	1509	0	2510	212	4653	162560	148	1135	0	0	5020	0	0	2	16	0	3	3	80210	80004	160000	80010	80145	80149	80219	80315	80295
160024	80278	600	3	0	0	0	0	0	0	9936	112	2344	1	0	0	1304	11	252	80095	2296	479	527	26	25	240014	80014	160000	80010	160000	400061	3688520	1	10	4	80133	80169	80234	60158	3	60139	240010	20	160000	20	320000	80091	80109	1	1	80021	10	9	10	10	80000	80000	10	162512	3	812	2499	0	2496	160079	1532	0	2518	212	4632	162569	79	755	0	0	5020	0	0	3	16	0	3	3	80237	80004	160000	80010	80205	80194	80134	80145	80140
160024	80211	601	2	0	0	0	0	0	0	9615	194	2349	1	0	0	1416	9	288	80135	2310	516	458	29	25	240014	80014	160000	80010	160000	400061	3686744	0	10	4	80115	80138	80162	60103	3	60066	240010	20	160000	20	320000	80163	80101	1	1	80021	10	9	10	10	80000	80000	10	162490	5	1506	2479	1	2488	160161	1505	0	2510	50	4864	162608	68	1058	0	0	5020	10	8	3	16	0	3	3	80228	80004	160000	80010	80303	80114	80222	80274	80148
160024	80176	601	2	2	0	0	0	0	0	9921	218	2352	1	0	0	1016	14	256	80115	2276	811	830	87	25	240014	80014	160000	80010	160000	400061	3682928	0	10	4	80139	80186	80143	60165	3	60174	240010	20	160000	20	320000	80137	80118	1	1	80021	10	9	10	10	80000	80000	10	162518	9	544	2458	7	2506	160104	1488	0	2509	262	4671	162574	133	2036	0	0	5020	10	8	3	16	0	3	3	80240	80004	160000	80010	80210	80204	80096	80257	80242
160024	80090	600	2	2	0	0	0	0	0	9783	194	2300	1	0	0	1504	13	468	80251	2231	859	1011	55	25	240014	80014	160000	80066	160000	400061	3688232	1	10	4	80253	80266	80180	60163	3	60188	240010	20	160000	20	320000	80286	80246	1	1	80021	10	9	10	10	80000	80000	10	162472	16	2195	2456	1	2476	160101	1501	0	2484	478	4593	162608	142	1804	0	0	5020	0	0	3	16	0	3	3	80259	80004	160000	80010	80254	80249	80255	80180	80197
160024	80208	601	3	3	0	0	3	0	0	9783	206	2346	1	0	0	1512	17	236	80275	2244	799	711	37	25	240014	80014	160000	80010	160000	400061	3687344	0	10	4	80155	80222	80198	60183	3	60196	240010	20	160000	20	320000	80242	80223	1	1	80021	10	9	10	10	80000	80000	10	162488	13	2145	2428	1	2466	160127	1510	0	2492	498	4634	162596	121	2224	0	0	5020	0	0	3	16	0	3	3	80243	80004	160000	80010	80240	80189	80289	80274	80232
160024	80196	601	3	4	0	0	0	0	0	10020	191	2297	1	0	0	1528	25	272	80228	2263	809	1224	59	25	240014	80014	160000	80010	160000	400061	3688064	0	10	4	80288	80275	80223	60180	3	60137	240010	20	160000	20	320000	80267	80241	1	1	80021	10	9	10	10	80000	80000	10	162492	23	1206	2440	7	2524	160123	1472	4	2488	514	4674	162613	145	2239	0	0	5020	10	0	2	16	0	2	3	80311	80004	160000	80010	80291	80278	80283	80324	80262
160024	80247	602	4	4	0	0	4	0	0	9720	168	2297	1	0	0	1280	10	172	80138	2324	1178	440	51	25	240014	80014	160000	80010	160000	400061	3684920	0	10	4	80232	80134	80177	60264	3	60180	240010	20	160000	20	320000	80147	80179	1	1	80021	10	9	10	10	80000	80000	10	162486	21	2493	2439	3	2489	160088	1507	0	2510	212	4606	162621	61	1381	0	0	5020	0	0	3	16	0	3	3	80120	80004	160000	80010	80289	80160	80246	80212	80198

STP (pre-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations