Firestorm: STP (pre-index, S) measurements

Code:

  stp s0, s1, [x6, #0x10]!
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
9006	1166	9	0	2	0	5	30	1	0	16	0	1151	18	1	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1012	8	35	0	0	1000	0	0	0	3	1004	4	23	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	6	5	28	1	0	16	0	1151	14	1	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1026	0	39	3	16	1004	1	40	14	4	1020	4	12	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	7	24	1	0	10	0	1151	4	1	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1022	0	23	2	16	1004	0	16	30	4	1036	4	23	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	6	22	1	0	12	0	1151	18	1	1	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	0	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	0	28	0	0	1004	0	0	0	0	1004	4	16	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	7	14	1	0	11	0	1151	4	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1042	0	24	4	24	1004	0	24	18	4	1026	4	19	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	0	0	7	16	1	0	21	16	1151	0	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1038	0	28	1	22	1004	0	16	8	4	1033	4	27	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	12	6	4	1	0	12	4	1151	8	4	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1269	1166	1	1	8001	1000	1000	1014	0	31	5	6	1003	1	38	28	0	1026	4	31	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	5	12	0	0	14	20	1151	14	0	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1016	0	27	4	16	1003	1	12	0	6	1028	0	43	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	0	0	7	38	1	0	13	0	1151	12	1	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	1	1145	1166	1166	3	24	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1022	0	23	1	6	1007	0	8	0	4	1028	4	12	510	16	1163	1000	0	0	1000	1000	1000	1229	1170	1167	1167	1167
9004	1166	9	0	0	6	5	28	1	0	11	0	1151	12	1	0	25	3000	1000	1000	1000	1000	1000	1000	5999	10875	8000	0	0	1145	1166	1166	3	25	3000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1014	0	19	1	24	1000	0	44	28	4	1028	0	27	510	16	1163	1000	0	0	1000	1000	1000	1167	1167	1167	1167	1167

Test 2: Latency 3->3

Code:

  stp s0, s1, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	37	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20224	10040	75	2	2	0	2	0	0	10470	51	2249	1	1448	130	5	1	944	10148	2217	0	160	176	36	25	30241	10100	10023	10000	10100	10000	10000	543912	468848	80410	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12495	16	1697	1474	0	1452	11020	1533	0	2493	50	4647	12502	26	697	0	0	710	1	16	1	1	10037	10000	177	2	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	76	3	0	3	3	0	0	10260	72	2306	1	1728	141	6	0	932	10025	2306	0	226	221	35	25	30231	10100	10123	10000	10100	10000	10000	543979	468848	80237	0	10017	10040	10040	7424	3	7498	30100	202	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12479	15	1723	1460	0	1458	11027	1528	2	2485	50	4619	12496	21	583	0	0	710	1	16	1	1	10037	10000	241	4	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	0	0	0	0	0	10335	62	2321	1	1496	161	12	1	944	10025	2264	0	226	190	28	25	30221	10100	10123	10000	10100	10000	10000	543959	468848	80410	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12501	24	1741	1291	0	1501	11037	1506	3	2505	50	4536	12500	28	758	0	0	710	1	16	1	1	10037	10000	283	0	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	3	0	3	0	0	10266	62	2259	1	1248	184	7	0	736	10025	2278	0	183	205	40	25	30239	10100	10102	10000	10100	10000	10000	543935	468848	80057	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12481	24	1750	1465	0	1477	11065	1518	3	2493	50	4646	12510	26	707	7	0	710	1	16	1	1	10037	10000	323	0	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	3	0	3	0	0	10455	67	2306	1	1400	212	7	1	780	10025	2253	0	177	183	41	25	30196	10100	10113	10000	10100	10000	10000	543939	468848	80390	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12465	24	1662	1483	0	1464	11050	1494	0	2485	50	4499	12494	27	752	0	9	710	1	16	1	1	10037	10000	329	3	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	76	3	0	0	0	0	0	10242	63	2256	1	1480	137	10	2	944	10025	2224	2	210	187	42	25	30250	10100	10097	10000	10100	10000	10000	543951	468848	80497	1	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12489	26	1748	1394	0	1475	11024	1516	0	2485	50	4582	12497	27	748	0	0	710	1	16	1	1	10037	10000	225	4	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	3	0	3	0	0	10269	77	2278	1	1488	171	11	1	840	10025	2261	0	234	175	42	25	30254	10100	10131	10000	10100	10000	10000	543967	468848	80258	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12484	24	1721	1503	0	1432	11064	1498	3	2457	50	4538	12482	25	848	0	3	710	1	16	1	1	10037	10000	229	5	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	0	0	3	0	0	10392	68	2278	1	1520	140	9	0	1032	10025	2255	0	184	206	24	25	30224	10100	10137	10000	10100	10000	10000	543967	468848	80187	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12484	24	1737	1469	0	1509	11017	1502	3	2493	50	4507	12487	27	628	0	3	710	1	16	1	1	10037	10000	214	0	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	76	3	3	0	0	0	0	10506	67	2286	1	1488	197	10	0	704	10025	2250	0	199	224	38	25	30248	10100	10155	10000	10100	10000	10000	543947	468848	80621	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12493	27	1663	1475	1	1480	11063	1514	0	2489	50	4543	12499	25	784	0	0	710	1	16	1	1	10037	10000	394	10	1	10000	10000	10100	10041	10041	10041	10041	10041
20204	10040	75	3	0	0	3	0	0	10497	58	2294	1	1688	125	7	2	736	10025	2262	0	222	174	29	25	30241	10100	10140	10000	10100	10000	10000	543920	468848	80500	0	10017	10040	10040	7424	3	7498	30100	200	10000	10000	200	20000	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	23	1753	1471	0	1446	11048	1512	0	2505	50	4502	12487	25	805	0	3	710	1	16	1	1	10037	10000	239	0	1	10000	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	20	22	29	37	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20044	10040	75	3	3	0	0	0	10413	66	2225	1	2224	336	12	0	212	10025	2165	262	211	39	25	30106	10010	10430	10000	10010	10000	10000	543409	468848	81114	0	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12489	31	1626	1622	0	1674	10840	1470	8	2497	50	4543	12490	33	717	0	0	640	6	16	6	5	10037	10000	387	4	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	76	4	4	0	0	0	10371	59	2211	1	2224	494	14	0	212	10025	2165	212	225	41	25	30554	10010	10014	10000	10010	10000	10000	543397	468848	81606	1	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12481	26	1559	1648	0	1670	10830	1528	4	2489	50	4573	12496	31	910	0	4	640	5	16	5	6	10037	10000	405	4	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	5	5	0	0	0	10386	82	2218	1	2224	425	15	0	212	10025	2172	214	198	43	25	30027	10010	10223	10000	10010	10000	10000	543345	468848	81489	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12502	40	1565	1670	0	1701	10815	1529	0	2489	50	4514	12487	29	728	0	0	640	7	16	6	7	10037	10000	235	5	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	5	0	0	0	0	10305	63	2190	1	2224	16	18	2	212	10025	2165	242	226	57	25	30536	10010	10279	10000	10010	10000	10000	543393	468848	80045	0	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12481	32	1568	1648	0	1707	10840	1505	0	2497	50	4617	12494	33	760	0	10	640	7	16	6	6	10037	10000	401	3	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	5	5	0	0	0	10407	63	2218	1	2240	534	16	0	212	10025	2165	224	232	101	25	30659	10010	10023	10000	10010	10000	10000	543329	468848	80860	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20240	20240	10164	10040	1	1	10021	10	9	10	10	10000	10000	10	12486	35	1583	1643	0	1674	10831	1467	10	2481	50	4531	12479	31	773	0	5	640	7	16	6	6	10037	10000	307	9	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	4	4	0	0	0	10593	62	2204	1	2208	42	8	0	212	10025	2165	202	243	35	25	30659	10010	10643	10000	10010	10000	10000	543377	468848	80754	0	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12465	27	1684	1652	0	1682	10841	1528	4	2489	50	4559	12492	42	802	0	4	640	5	16	5	5	10037	10000	231	3	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	4	0	4	4	0	10182	66	2211	1	2208	546	12	0	212	10025	2158	258	225	33	25	30029	10010	10541	10000	10010	10000	10000	543361	468848	81925	1	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12497	35	1548	1639	0	1666	10819	1520	0	2489	50	4568	12475	39	703	0	10	640	6	15	6	6	10037	10000	284	4	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	5	0	0	5	0	10371	65	2211	1	2200	12	14	0	212	10025	2158	244	269	36	25	30271	10010	10311	10000	10010	10000	10000	543001	468848	81601	0	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12483	34	1492	1623	0	1680	10803	1513	0	2489	50	4555	12480	28	749	0	5	640	5	16	5	5	10037	10000	388	4	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	76	5	5	5	0	0	10176	61	2211	1	2216	650	13	0	212	10025	2165	204	225	40	25	30191	10010	10036	10000	10010	10000	10000	543385	468848	80876	0	10022	10040	10040	7446	3	7520	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12494	40	1746	1678	0	1688	10815	1503	0	2489	50	4579	12484	24	723	0	0	640	7	16	7	7	10037	10000	222	3	10000	10000	10010	10041	10041	10041	10041	10041
20024	10040	75	5	0	0	0	0	10362	73	2183	1	2224	6	16	0	212	10025	2165	171	231	41	25	30317	10010	10407	10000	10010	10000	10000	543353	468848	81307	1	10022	10040	10040	7446	3	7521	30010	20	10000	10000	20	20000	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12473	27	1489	1624	0	1690	10826	1494	0	2481	50	4574	12486	37	774	0	4	640	5	16	6	6	10037	10000	320	8	10000	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  stp s0, s1, [x6, #0x10]!
  stp s0, s1, [x7, #0x10]!
  stp s0, s1, [x8, #0x10]!
  stp s0, s1, [x9, #0x10]!
  stp s0, s1, [x10, #0x10]!
  stp s0, s1, [x11, #0x10]!
  stp s0, s1, [x12, #0x10]!
  stp s0, s1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5022

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	24	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160224	40097	301	2	2	2	0	0	0	10182	81	2385	2	0	0	1256	2822	9	772	40139	2296	645	358	22	25	243027	80102	82756	80000	80100	80000	80000	400531	1844848	650340	0	2	40131	40146	40129	20133	0	3	20085	240100	200	80000	80000	200	160000	160000	40139	40151	1	1	80201	100	99	100	100	80000	80000	100	82528	20	1242	2487	0	2491	80051	1548	0	2494	682	4688	82537	52	1165	14	0	0	0	0	0	5110	0	1	16	1	1	40137	80002	80000	80000	80100	40147	40117	40176	40130	40153
160204	40128	301	3	0	0	0	0	0	10086	356	2335	2	0	0	1288	2975	7	604	40150	2301	477	684	49	25	242719	80102	81311	80000	80100	80000	80000	400531	1842904	648327	0	2	40156	40411	40353	20067	0	3	20073	240100	200	80000	80000	200	160000	160000	40142	40129	1	1	80201	100	99	100	100	80000	80000	100	82578	40	2284	2458	9	2494	80074	1530	0	2474	942	4661	82530	78	1871	14	0	0	0	0	0	5110	0	1	16	1	1	40110	80002	80000	80000	80100	40175	40107	40155	40159	40166
160204	40128	300	2	2	2	2	0	0	9855	69	2354	2	0	0	1288	1510	6	700	40116	2296	575	584	50	25	242012	80102	82563	80000	80100	80000	80000	400531	1843624	646038	0	2	40169	40126	40165	20106	0	3	20099	240100	200	80000	80000	200	160000	160000	40161	40117	1	1	80201	100	99	100	100	80000	80000	100	82503	16	1486	2470	11	2487	80056	1540	0	2496	558	4747	82540	49	1437	14	0	0	0	0	0	5110	0	1	16	1	1	40120	80002	80000	80000	80100	40108	40148	40108	40144	40359
160204	40343	302	2	2	0	2	0	1	10452	469	2330	2	0	0	1288	1421	8	744	40111	2353	629	430	10	84	241920	80102	82619	80000	80100	80000	80000	400531	1844248	644483	1	2	40070	40105	40109	20061	0	3	20282	240100	200	80120	80000	200	160000	160000	40189	40130	1	1	80201	100	99	100	100	80000	80000	100	82587	18	1611	2486	0	2480	80048	1515	0	2478	520	4574	82764	63	1192	14	0	0	0	0	0	5110	0	1	16	1	1	40346	80002	80000	80000	80100	40124	40149	40166	40152	40149
160204	40145	300	2	0	0	0	0	0	9975	79	2336	4	0	0	1136	1847	9	708	40119	2295	590	533	23	25	242086	80102	83688	80000	80100	80000	80000	400531	1842928	645393	1	2	40086	40111	40176	20080	0	3	20159	240100	200	80000	80000	200	160000	160000	40155	40137	1	1	80201	100	99	100	100	80000	80000	100	82509	18	1107	2456	2	2496	80048	1530	4	2490	996	4641	82541	57	1321	14	3	0	0	0	0	5110	0	1	16	1	1	40132	80002	80000	80000	80100	40212	40098	40171	40156	40163
160204	40118	301	2	2	0	0	0	0	9759	77	2365	2	0	0	1040	2938	8	772	40099	2363	501	519	31	25	243810	80102	83154	80000	80100	80000	80000	400531	1846192	647588	0	2	40091	40144	40112	20200	0	3	20049	240100	200	80000	80000	200	160000	160000	40115	40145	1	1	80201	100	99	100	100	80000	80000	100	82496	16	1460	2493	0	2483	80057	1521	4	2474	726	4625	82533	76	1412	14	0	0	0	0	0	5110	0	1	16	1	1	40126	80002	80000	80000	80100	40136	40118	40125	40131	40152
160204	40122	302	2	2	2	0	0	0	9945	91	2359	2	0	0	1040	1425	5	844	40085	2299	668	594	44	25	241091	80102	82601	80000	80100	80000	80000	400531	1845568	645146	1	2	40112	40142	40135	20055	0	3	20073	240100	200	80000	80000	200	160000	160000	40116	40134	1	1	80201	100	99	100	100	80000	80000	100	82522	18	1250	2484	2	2493	80050	1536	0	2496	704	4625	82537	59	1499	14	3	0	0	0	0	5110	0	1	16	1	1	40115	80002	80000	80000	80100	40125	40139	40125	40152	40145
160204	40122	301	2	0	2	0	0	0	9909	88	2363	2	0	0	888	1142	4	668	40097	2294	546	743	40	25	241604	80102	82962	80000	80100	80000	80000	400531	1844320	647114	1	2	40079	40155	40151	20045	0	3	20098	240100	200	80000	80000	200	160000	160000	40149	40149	1	1	80201	100	99	100	100	80000	80000	100	82519	16	1107	2477	3	2501	80062	1516	0	2496	546	4713	82547	57	1188	14	4	0	0	0	0	5110	0	1	16	1	1	40121	80002	80000	80000	80100	40145	40140	40121	40116	40158
160204	40141	301	2	0	2	0	0	0	9483	81	2357	2	0	0	1056	3195	10	656	40089	2312	716	542	26	25	242814	80102	81622	80000	80100	80000	80000	400531	1844224	646287	1	2	40087	40144	40126	20042	0	3	20108	240100	200	80000	80000	200	160000	160000	40141	40127	1	1	80201	100	99	100	100	80000	80000	100	82507	16	1161	2489	14	2491	80047	1534	2	2490	428	4634	82550	53	1255	14	4	0	0	0	0	5110	0	1	16	1	1	40177	80002	80000	80000	80100	40153	40148	40138	40145	40143
160204	40125	300	2	0	2	0	0	0	10128	68	2312	2	0	0	1272	3102	6	692	40134	2285	431	522	45	25	242834	80102	83471	80000	80100	80000	80000	400531	1844224	648143	1	2	40127	40139	40154	20046	0	3	20077	240100	200	80000	80000	200	160000	160000	40118	40143	1	1	80201	100	99	100	100	80000	80000	100	82526	16	1193	2494	0	2498	80055	1553	2	2500	370	4671	82538	68	1040	14	3	0	0	0	0	5110	0	1	16	1	1	40137	80002	80000	80000	80100	40133	40137	40140	40189	40122

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5021

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	24	29	37	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	67	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160045	40170	300	0	2	0	2	2	2	0	0	10176	72	2278	1	0	1656	952	4	728	40206	2229	477	667	42	25	243530	80012	80432	80000	80010	80000	80000	400081	1843912	652832	0	0	2	40117	40411	40145	20068	0	3	20088	240010	20	80000	80000	20	160000	160000	40125	40108	1	1	80021	10	9	10	10	80000	80000	10	82490	27	2053	2457	4	2499	80057	1523	0	2484	938	4652	82508	43	1504	14	0	0	5020	0	0	11	16	7	10	40184	80002	80000	80000	80010	40142	40153	40139	40132	40175
160024	40134	300	0	2	0	2	2	0	0	0	10137	62	2323	1	0	1696	2596	6	728	40130	2320	524	490	58	25	241960	80012	83935	80000	80010	80000	80000	400081	1844272	643719	0	0	2	40134	40206	40215	20127	0	3	20161	240010	20	80000	80000	20	160000	160000	40158	40152	1	1	80021	10	9	10	10	80000	80000	10	82502	16	2172	2417	9	2464	80055	1496	0	2500	254	4621	82505	39	1515	14	0	0	5020	0	0	11	16	12	11	40148	80002	80000	80000	80010	40156	40131	40195	40184	40133
160024	40162	300	0	2	0	0	0	0	0	0	10110	85	2298	1	0	1664	789	3	556	40131	2270	596	652	46	25	240128	80012	80120	80000	80010	80000	80000	400081	1844128	647912	0	0	2	40130	40168	40175	20087	0	3	20132	240010	20	80000	80000	20	160000	160000	40143	40167	1	1	80021	10	9	10	10	80000	80000	10	82491	20	1328	2440	2	2453	80055	1514	0	2475	254	4625	82504	46	1157	14	2	0	5020	0	0	11	16	10	10	40130	80002	80000	80000	80010	40183	40147	40142	40175	40214
160024	40187	301	0	2	0	0	2	2	0	0	10116	76	2290	1	0	1608	1230	5	728	40106	2224	339	540	30	25	242534	80012	82675	80000	80010	80000	80000	400081	1845880	640313	0	0	2	40204	40199	40200	20089	0	3	20173	240010	20	80000	80000	20	160000	160000	40136	40153	1	1	80021	10	9	10	10	80000	80000	10	82500	16	1452	2438	3	2485	80053	1516	0	2472	254	4646	82509	65	1343	14	2	0	5020	0	0	11	16	10	10	40382	80002	80000	80000	80010	40171	40172	40168	40169	40146
160024	40134	300	0	2	0	2	0	2	0	0	10158	48	2275	3	0	1656	435	5	1016	40203	2264	466	635	48	25	241016	80012	84005	80000	80010	80000	80000	400081	1845328	649074	1	0	2	40145	40155	40143	20084	0	3	20090	240010	20	80000	80000	20	160000	160000	40116	40177	1	1	80021	10	9	10	10	80000	80000	10	82486	16	1690	2467	12	2460	80057	1500	0	2484	254	4734	82516	38	1733	14	0	0	5020	0	0	10	16	10	10	40132	80002	80000	80000	80010	40190	40201	40174	40184	40184
160024	40159	301	0	2	0	0	2	2	0	0	10008	69	2285	1	0	1512	2381	5	556	40202	2241	455	698	59	25	240438	80012	82993	80000	80010	80000	80000	400081	1845448	651966	0	0	2	40069	40188	40133	20071	0	3	20153	240010	20	80000	80000	20	160000	160000	40117	40163	1	1	80021	10	9	10	10	80000	80000	10	82494	18	1752	2459	10	2482	80050	1531	2	2468	252	4661	82510	54	936	14	0	0	5020	0	0	10	16	10	9	40143	80002	80000	80000	80010	40174	40145	40166	40128	40206
160024	40181	301	0	2	0	0	2	0	0	0	10041	80	2304	1	0	1504	999	6	728	40134	2276	501	563	45	25	242638	80012	84328	80000	80010	80000	80000	400081	1844920	653951	1	0	2	40177	40190	40148	20126	0	3	20140	240010	20	80000	80000	20	160000	160000	40201	40138	1	1	80021	10	9	10	10	80000	80000	10	82497	16	1329	2427	6	2474	80059	1523	4	2479	254	4607	82530	60	1403	14	0	0	5020	0	0	11	16	9	6	40133	80002	80000	80000	80010	40159	40145	40136	40165	40114
160024	40176	300	0	1	0	0	1	0	0	0	9942	66	2290	1	0	1520	1660	4	556	40187	2270	633	485	62	25	241394	80012	83782	80000	80010	80000	80000	400081	1845016	640386	1	0	2	40161	40113	40211	20100	0	3	20146	240010	20	80000	80000	20	160000	160000	40120	40170	1	1	80021	10	9	10	10	80000	80000	10	82482	16	1663	2456	3	2472	80052	1510	2	2472	250	4580	82509	53	1728	14	0	0	5020	0	0	10	16	10	10	40144	80002	80000	80000	80010	40196	40140	40195	40189	40192
160024	40171	301	0	2	0	0	2	2	0	0	10092	76	2291	3	0	1624	695	7	576	40141	2256	480	420	47	25	241637	80012	82006	80000	80010	80000	80000	400081	1843792	652141	1	0	2	40131	40183	40160	20083	0	3	20118	240010	20	80000	80000	20	160000	160000	40140	40147	1	1	80021	10	9	10	10	80000	80000	10	82494	16	1744	2460	7	2459	80049	1534	0	2476	254	4651	82517	46	1581	14	0	0	5020	0	0	11	16	11	10	40165	80002	80000	80000	80010	40136	40158	40170	40153	40160
160024	40131	301	0	2	0	2	0	0	0	0	9861	89	2296	1	0	1472	172	4	708	40189	2267	586	546	38	25	241538	80012	83039	80000	80010	80000	80000	400081	1843048	641499	0	0	2	40098	40174	40158	20072	0	3	20130	240010	20	80000	80000	20	160000	160000	40161	40153	1	1	80021	10	9	10	10	80000	80000	10	82502	20	1271	2470	13	2484	80032	1514	0	2476	250	4593	82509	45	1349	14	0	0	5020	0	0	10	16	11	10	40116	80002	80000	80000	80010	40189	40160	40189	40186	40184

STP (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations