Firestorm: STP (signed offset, D) measurements

Code:

  stp d0, d1, [x6, #0x10]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	10	0	1	1	0	1151	7	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	16	1000	0	0	1000	1	15	512	2	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	2	2	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	3	1000	0	15	513	2	16	2	2	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	513	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	0	1	1	0	1151	8	8	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	15	1000	0	0	1000	0	15	512	1	16	1	1	1163	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]
  stp d0, d1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	22	24	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	40058	299	1	1	0	0	0	132	19	1	0	2634	1	40035	16	16	0	25	163236	100	82351	80000	100	80000	80000	500	1839952	649065	0	40025	40050	40061	19974	3	20018	160100	200	80000	80000	200	160000	160000	40058	40058	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	1	0	5	80002	2	34	0	0	0	5110	1	16	1	1	40039	80000	80000	100	40043	40043	40043	40044	40043
160204	40049	299	0	0	0	0	0	12	3	1	0	2857	0	40027	16	0	0	25	163461	100	81744	80000	100	80000	80000	500	1839856	650981	0	40021	40043	40042	19959	3	20001	160100	200	80000	80000	200	160000	160000	40042	40252	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	0	0	80002	2	34	0	0	0	5110	1	16	1	1	40040	80000	80000	100	40044	40043	40043	40043	40043
160204	40042	300	0	0	0	0	4	0	0	0	0	3795	0	40027	16	16	0	25	163894	100	82687	80000	100	80000	80000	500	1839712	652884	0	40021	40042	40042	19961	3	20001	160100	200	80000	80000	200	160000	160000	40049	40281	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	0	2	80000	0	0	0	0	0	5110	1	16	1	1	40040	80000	80000	100	40044	40043	40043	40044	40043
160204	40048	300	0	0	0	0	0	0	0	0	0	4366	0	40027	16	16	0	25	163151	100	81684	80000	100	80000	80000	500	1839712	649899	0	40021	40042	40042	19962	3	20001	160100	200	80000	80000	200	160000	160000	40043	40049	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	0	0	80002	0	34	0	0	0	5110	1	16	1	1	40040	80000	80000	100	40050	40059	40053	40059	40048
160204	40058	300	1	1	1	1	0	0	14	0	0	3315	1	40043	16	16	3	25	163839	100	82137	80000	100	80000	80000	500	1840000	649702	0	40025	40050	40059	19963	3	20009	160100	200	80000	80000	200	160000	160272	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	0	0	80002	0	34	0	0	1	5110	1	16	1	1	40040	80000	80000	100	40053	40051	40053	40050	40051
160204	40059	300	1	0	0	1	0	0	21	0	0	3210	1	40043	16	16	5	25	161446	100	82348	80000	100	80000	80000	500	1839904	650974	0	40027	40058	40058	19963	3	20007	160100	200	80000	80000	200	160000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	2	80014	0	0	14	80002	16	36	14	0	0	5110	1	16	1	1	40047	80000	80000	100	40051	40051	40058	40052	40059
160204	40052	300	1	1	0	1	0	0	21	0	0	328	1	40035	16	16	3	25	162989	100	82154	80000	100	80000	80000	500	1839928	651069	0	40025	40050	40061	19971	3	20010	160100	200	80000	80000	200	160000	160000	40058	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	16	36	1	80016	0	1	20	80002	14	36	14	0	0	5110	1	16	1	1	40047	80000	80000	100	40043	40043	40044	40043	40044
160204	40049	300	0	0	0	0	0	0	3	0	0	4382	0	40027	16	16	0	25	163769	100	81684	80000	100	80000	80000	500	1839712	651775	0	40021	40048	40043	19959	3	20000	160100	200	80000	80000	200	160000	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	2	80016	0	2	17	80000	16	0	14	1	0	5110	1	16	1	1	40047	80000	80000	100	40044	40049	40043	40044	40043
160204	40042	300	0	0	0	0	0	0	3	0	0	3592	0	40028	16	16	0	25	163236	100	80294	80000	100	80000	80000	500	1839712	651540	0	40021	40042	40042	19959	3	20000	160100	200	80000	80000	200	160000	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	0	0	80002	2	0	0	0	0	5110	1	16	1	1	40039	80000	80000	100	40049	40044	40050	40043	40043
160204	40042	299	0	0	0	0	0	0	0	0	0	1646	0	40034	16	16	6	25	163224	100	84373	80000	100	80000	80000	500	1839712	653166	0	40021	40048	40042	19959	3	20000	160100	200	80000	80000	200	160000	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	0	2	80002	0	0	0	0	0	5110	1	16	1	1	40040	80000	80000	100	40043	40043	40043	40044	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	37	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	40054	300	1	0	1	0	0	1	0	0	0	20	1	2371	1	40048	16	16	1	25	160856	10	84347	80000	10	80000	80000	50	1840504	648565	40025	40052	40054	19988	0	3	20030	160010	20	80000	80000	20	160000	160000	40050	40051	1	1	80021	10	9	10	10	80000	80000	10	80014	14	44	0	1	80016	1	1	17	80002	14	0	14	1	5020	23	16	23	23	40048	80000	80000	10	40052	40055	40052	40055	40053
160024	40054	300	1	0	1	1	0	1	0	0	0	19	0	2371	1	40039	0	16	2	25	162221	10	82963	80000	10	80000	80000	50	1840480	640109	40028	40054	40063	19988	0	3	20032	160010	20	80000	80000	20	160000	160000	40050	40054	1	1	80021	10	9	10	10	80000	80000	10	80015	14	44	0	0	80016	0	0	21	80002	16	44	14	0	5020	22	16	23	23	40051	80000	80000	10	40051	40052	40055	40049	40051
160024	40047	299	1	0	0	1	0	1	0	0	0	14	0	3462	1	40035	0	16	1	25	160063	10	83939	80000	10	80000	80000	50	1840072	647129	40028	40050	40062	19998	0	3	20031	160010	20	80000	80000	20	160000	160000	40054	40063	1	1	80021	10	9	10	10	80000	80000	10	80015	16	0	0	1	80016	1	1	17	80002	16	0	14	0	5020	20	16	24	19	40059	80000	80000	10	40054	40055	40056	40053	40054
160024	40062	299	1	0	1	0	0	0	0	0	18	19	1	4093	1	40039	0	16	1	25	160059	10	81690	80000	10	80000	80000	50	1840072	647132	40025	40053	40052	19986	0	3	20028	160010	20	80000	80000	20	160000	160000	40050	40050	1	1	80021	10	9	10	10	80000	80000	10	80015	14	44	0	1	80014	0	0	14	80002	14	44	14	0	5020	23	16	23	25	40047	80000	80000	10	40055	40049	40055	40054	40055
160024	40048	300	1	0	1	0	0	0	0	0	0	14	1	3227	1	40039	16	16	1	25	160053	10	80029	80000	10	80000	80000	50	1839904	642538	40025	40050	40062	19986	0	3	20028	160010	20	80000	80000	20	160000	160000	40054	40062	1	1	80021	10	9	10	10	80000	80000	10	80015	14	44	0	0	80016	0	1	14	80002	16	44	14	0	5020	23	16	21	23	40047	80000	80000	10	40054	40051	40063	40055	40051
160024	40049	300	1	0	0	0	0	0	0	0	0	22	1	2377	1	40037	0	0	0	25	160046	10	84133	80000	10	80000	80000	50	1840096	653973	40029	40052	40048	19983	0	3	20033	160010	20	80000	80000	20	160000	160000	40051	40052	1	1	80021	10	9	10	10	80000	80000	10	80014	15	42	2	0	80016	0	1	19	80002	14	44	14	0	5020	23	16	20	22	40047	80000	80000	10	40055	40053	40051	40050	40055
160024	40047	300	1	0	0	0	0	0	0	0	0	17	0	4044	1	40039	16	16	0	36	164921	10	82500	80000	10	80000	80000	50	1839904	640184	40028	40063	40052	19987	0	3	20030	160010	20	80000	80000	20	160000	160000	40050	40048	1	1	80021	10	9	10	10	80000	80000	10	80016	15	0	3	0	80014	1	0	20	80000	16	0	14	0	5020	23	16	14	22	40059	80000	80000	10	40053	40053	40055	40051	40052
160024	40050	300	1	0	1	1	0	0	0	0	0	18	1	69	1	40035	0	16	1	25	163468	10	83975	80000	10	80000	80000	50	1840000	647140	40026	40054	40054	19986	0	3	20028	160010	20	80000	80000	20	160000	160000	40054	40053	1	1	80021	10	9	10	10	80000	80000	10	80015	14	44	0	1	80016	0	0	16	80002	16	0	14	0	5020	24	16	26	25	40060	80000	80000	10	40055	40048	40055	40053	40055
160024	40051	300	1	0	1	1	0	1	0	0	0	17	0	4049	1	40036	0	16	1	25	163663	10	84117	80000	10	80000	80000	50	1839928	643766	40026	40054	40054	19989	0	3	20042	160010	20	80000	80000	20	160000	160000	40053	40054	1	1	80021	10	9	10	10	80000	80000	10	80014	16	44	0	0	80014	0	1	16	80002	16	0	14	0	5020	23	16	18	23	40052	80000	80000	10	40051	40052	40051	40052	40055
160024	40052	300	1	0	1	1	0	0	0	0	0	19	1	2618	1	40037	16	16	0	25	162168	10	80049	80000	10	80000	80000	50	1840000	648539	40023	40050	40052	19990	0	3	20031	160010	20	80000	80000	20	160000	160276	40054	40054	1	1	80021	10	9	10	10	80000	80000	10	80015	15	44	0	1	80016	0	2	19	80000	16	44	14	1	5020	23	16	12	23	40051	80000	80000	10	40053	40055	40063	40051	40055

STP (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations