Firestorm: STP (signed offset, Q) measurements

Code:

  stp q0, q1, [x6, #0x10]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	24	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
9005	1165	9	0	3	1	0	1150	14	14	25	2000	2000	2000	10017	0	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2002	0	2000	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	7	1	0	1150	14	14	25	2000	2000	2000	10017	0	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	1	2000	9	2002	2	38	2	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	3	0	0	1150	14	14	25	2000	2000	2000	10000	1	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2002	2	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	3	1	0	1150	14	14	25	2000	2000	2000	10017	1	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2002	2	2000	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	171	11	1	0	1150	14	14	25	2000	2000	2000	10016	0	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2002	2	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	0	1	0	1150	14	14	25	2000	2000	2000	10017	1	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	1	2000	6	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	15	3	0	0	1150	14	14	25	2000	2000	2000	10016	0	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2000	2	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	8	0	3	1	0	1150	0	14	25	2000	2000	2000	10017	1	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	0	1	2002	6	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	21	10	1	0	1150	14	14	25	2000	2000	2000	10016	1	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2000	9	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166
9004	1165	9	0	0	1	0	1150	14	14	25	2000	2000	2000	10699	0	1140	0	1165	1165	3	23	2000	2000	4000	1165	1165	1	1	8001	1000	1000	2000	38	0	2002	2	2002	2	38	0	512	1	16	1	1	1162	2000	1166	1166	1166	1166	1166

Count: 8

Code:

  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]
  stp q0, q1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80042	599	0	0	0	0	3	0	80027	16	0	0	25	160100	100	160000	100	160007	500	3679455	0	80015	80042	80050	59961	7	59992	160107	200	160016	200	320032	80042	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160002	0	0	5	160000	2	0	1	1	1	5117	0	16	0	0	80047	160000	100	80043	80043	80041	80041	80043
160204	80040	600	0	0	0	0	6	0	80027	16	16	0	25	160100	100	160000	100	160006	500	3679455	0	80015	80049	80040	59969	7	59992	160106	200	160016	200	320032	80040	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160002	0	0	2	160000	0	0	1	1	1	5117	0	16	0	0	80039	160000	100	80043	80043	80051	80041	80052
160204	80042	599	0	0	0	0	3	1	80027	0	16	0	25	160100	100	160000	100	160007	500	3679378	0	80026	80040	80040	59970	7	59994	160107	200	160016	200	320032	80042	80040	2	1	80201	100	99	100	100	80000	80000	100	160000	0	160000	0	0	0	160002	2	34	1	1	1	5117	0	16	0	0	80039	160000	100	80041	80051	80052	80043	80043
160204	80040	599	0	0	0	0	3	1	80027	16	16	0	25	160100	100	160000	100	160007	500	3679455	0	80017	80042	80051	59959	7	59992	160107	200	160016	200	320032	80050	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160002	0	0	8	160002	2	34	1	1	1	5117	0	16	0	0	80037	160000	100	80041	80041	80043	80041	80051
160204	80040	599	0	0	0	0	0	1	80027	16	0	0	25	160100	100	160000	100	160006	500	3679455	0	80015	80040	80050	59955	3	60000	160100	200	160000	200	320000	80042	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160002	0	0	0	160002	2	34	0	0	0	5110	1	16	1	1	80037	160000	100	80043	80041	80041	80043	80043
160204	80042	599	0	0	0	0	3	0	80025	0	16	0	25	160100	100	160000	100	160000	500	3679784	0	80015	80042	80042	59963	3	59998	160100	200	160000	200	320000	80049	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160000	0	0	0	160002	0	0	0	0	0	5110	1	16	1	1	80037	160000	100	80043	80043	80041	80041	80051
160204	80049	599	0	0	0	0	3	1	80027	0	16	0	25	160100	100	160000	100	160000	500	3679424	0	80017	80040	80040	59953	3	59998	160100	200	160000	200	320000	80051	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	160002	0	0	5	160002	0	0	0	0	0	5110	1	16	1	1	80039	160000	100	80043	80041	80043	80041	80043
160204	80040	599	0	0	0	0	3	1	80027	16	16	2	25	160100	100	160000	100	160000	500	3679424	0	80025	80040	80042	59962	3	60000	160100	200	160000	200	320000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160002	0	0	2	160000	0	34	0	0	0	5110	1	16	1	1	80039	160000	100	80043	80050	80051	80043	80043
160204	80042	599	0	0	0	0	3	0	80034	16	0	0	25	160100	100	160000	100	160000	500	3679352	0	80017	80050	80042	59955	3	59998	160100	200	160000	200	320000	80050	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	34	160002	0	0	2	160002	0	34	0	0	0	5110	1	16	1	1	80037	160000	100	80189	80043	80043	80043	80043
160204	80040	599	1	0	0	0	3	0	80027	16	16	0	25	160100	100	160000	100	160000	500	3679424	0	80025	80040	80042	59964	3	59998	160100	200	160000	200	320000	80051	80042	1	1	80201	100	99	100	100	80000	80000	100	160000	0	160002	0	0	8	160000	2	0	0	0	0	5110	1	16	1	1	80046	160000	100	80050	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80059	599	0	0	0	0	0	0	0	3	1	0	0	80027	16	0	0	25	160010	10	160000	10	160432	50	3679832	1	80025	0	80040	80042	59975	3	60481	160010	20	160000	20	320000	80040	80051	1	1	80021	10	9	10	10	80000	80000	10	160016	14	36	0	1	160016	0	1	17	160000	16	36	14	1	0	5020	0	5	16	0	7	4	80047	160000	10	80048	80052	80050	80048	80060
160024	80058	599	1	1	0	0	0	0	324	18	1	0	1	80043	0	16	2	25	160010	10	160000	10	160000	50	3679692	1	80022	0	80052	80060	59993	3	60027	160010	20	160000	20	320000	80059	80060	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	2	0	0	160002	2	34	0	0	0	5020	0	5	43	0	5	5	80037	160000	10	80043	80043	80041	80052	80052
160024	80051	600	0	0	0	0	0	0	0	0	0	0	0	80025	16	16	298	25	160010	10	160000	10	160000	50	3679352	1	80017	0	80050	80040	59984	3	60020	160010	20	160480	20	320000	80040	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	1	0	2	160002	0	34	0	0	0	5020	0	6	34	0	6	6	80037	160000	10	80043	80043	80051	80052	80043
160024	80042	599	0	0	0	0	0	0	12	3	1	0	0	80027	16	16	5	25	160010	10	160000	10	160000	50	3679692	1	80033	0	80058	80603	59983	3	60030	160010	20	160000	20	320000	80058	80047	1	1	80021	10	9	10	10	80000	80000	10	160016	16	0	0	1	160014	0	0	3263	160002	16	0	14	2	0	5020	0	6	16	0	5	5	80049	160000	10	80051	80062	80049	80060	80060
160024	80059	600	1	0	0	1	0	0	0	14	0	0	1	80038	16	16	0	25	160010	10	160000	10	160000	50	3679352	1	80017	0	80042	80051	59975	3	60213	160010	20	160000	20	320240	80042	80050	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160002	0	0	2	160002	2	34	0	0	0	5020	0	5	16	0	7	7	80039	160000	10	80043	80041	80051	80043	80043
160024	80042	600	0	0	0	0	0	0	36	0	0	0	0	80594	16	16	0	25	160010	10	160000	10	160000	50	3679352	0	80015	0	80042	80051	59977	51	60022	160010	20	160000	20	320000	80042	80040	1	1	80021	10	9	10	10	80000	80000	10	160014	15	36	0	1	160016	0	1	17	160002	14	0	14	2	0	5020	0	5	16	0	6	9	80044	160000	10	80048	80048	80048	80054	80053
160024	80047	599	1	1	1	0	0	0	0	17	0	0	1	80601	16	16	5	25	160010	10	160000	10	160000	50	3679932	1	80027	0	80060	80058	60358	3	60027	160010	20	160000	20	320000	80060	80058	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	0	0	11	160002	2	34	0	0	0	5020	0	6	16	0	4	4	80039	160000	10	80191	80600	80597	80043	80043
160024	80040	599	0	0	0	1	0	0	0	3	1	0	0	80027	16	0	2	25	160190	10	160000	10	160000	50	3680246	0	80028	0	80047	80047	59982	3	60038	160442	20	160000	20	320000	80051	80618	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160002	1	2	2	160002	2	34	0	0	0	5020	0	6	16	0	5	5	80039	160000	10	80043	80043	80041	80051	80051
160024	80049	599	0	0	0	0	0	0	0	0	1	0	0	80027	16	16	0	25	160010	10	160000	10	160000	50	3679424	1	80017	0	80042	80040	59985	3	60022	160010	20	160000	20	320000	80040	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	34	0	0	160000	4	2	2	160000	2	34	0	0	0	5020	0	5	16	0	4	5	80046	160000	10	80048	80048	80059	80049	80051
160024	80611	599	1	1	1	0	0	0	0	19	1	0	1	80593	16	0	2	25	160010	10	160000	10	160000	50	3679352	1	80017	0	80042	80040	59977	3	60020	160010	20	160000	20	320000	80042	80042	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	0	0	160000	0	0	0	160002	2	34	0	0	0	5020	0	5	16	0	6	6	80037	160000	10	80043	80043	80043	80051	80041

STP (signed offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations