Firestorm: STP (signed offset, S) measurements

Code:

  stp s0, s1, [x6, #0x10]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1f	22	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
9006	1166	9	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	1	1	1001	1	19	519	12	16	11	11	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	3	1001	1	19	520	12	16	11	12	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	2	0	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	3	3	1001	1	19	519	12	16	11	11	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	1	1001	1	19	519	12	16	11	11	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	3	1001	1	19	519	11	16	11	12	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	1	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	3	1001	1	19	521	9	16	11	11	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	25	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	3	1001	1	19	520	10	16	10	11	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	9	2	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	1	1001	1	19	521	12	16	11	12	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	1	1001	1	19	519	12	16	12	11	1163	1000	1000	1167	1167	1167	1167	1167
9004	1166	8	4	1	1151	7	7	25	2000	1000	1000	1000	1000	10875	8000	0	1145	1166	1166	3	24	2000	1000	1000	2000	2000	1166	1166	1	1	8001	1000	1000	1000	19	1001	0	1	1001	1	19	521	11	16	11	12	1163	1000	1000	1167	1167	1167	1167	1167

Count: 8

Code:

  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]
  stp s0, s1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	22	37	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160206	40054	300	0	0	0	3	1	4289	40028	16	16	25	164389	100	84289	80000	100	80000	80000	500	1839712	643982	1	40021	40042	40043	19959	3	20001	160100	200	80000	80000	200	160000	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	2	80002	0	0	0	5110	1	16	1	1	40040	80000	80000	100	40043	40044	40044	40053	40044
160204	40042	299	0	0	0	3	0	1836	40027	0	16	25	164482	100	84380	80000	100	80000	80000	500	1839712	643982	1	40021	40043	40043	19959	3	20001	160100	200	80000	80000	200	160000	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80000	0	0	80000	0	42	0	5110	1	16	1	1	40041	80000	80000	100	40044	40043	40044	40043	40043
160204	40043	300	0	0	0	0	0	2220	40028	16	16	25	161424	100	81364	80000	100	80000	80000	500	1839712	643968	1	40021	40043	40043	19959	3	20000	160100	200	80000	80000	200	160000	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80000	1	0	80002	0	0	0	5110	1	16	1	1	40039	80000	80000	100	40043	40043	40044	40044	40043
160204	40043	300	0	0	0	0	0	4289	40027	16	16	25	163625	100	84382	80000	100	80000	80000	500	1839712	646680	1	40021	40043	40043	19959	3	20001	160100	200	80000	80000	200	160000	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	2	80002	2	0	0	5110	1	16	1	1	40039	80000	80000	100	40044	40043	40043	40043	40044
160204	40043	300	0	0	0	0	1	2222	40028	0	16	25	164482	100	83307	80000	100	80000	80000	500	1839712	649899	1	40021	40043	40043	19959	3	20000	160100	200	80000	80000	200	160000	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80000	0	0	80000	2	0	0	5110	1	16	1	1	40039	80000	80000	100	40044	40043	40044	40043	40044
160204	40043	300	0	0	0	3	1	4273	40028	0	16	25	162957	100	80666	80000	100	80000	80000	500	1839712	645529	0	40021	40042	40042	19959	3	20000	160100	200	80000	80000	200	160000	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	2	80002	2	42	0	5110	1	16	1	1	40040	80000	80000	100	40250	40044	40043	40046	40044
160204	40043	300	0	0	0	3	1	1109	40028	16	0	25	162289	100	84380	80000	100	80000	80000	500	1839712	648009	1	40021	40042	40042	19959	3	20000	160100	200	80000	80000	200	160000	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	0	2	80002	2	42	0	5110	1	16	1	1	40039	80000	80000	100	40043	40044	40044	40043	40044
160204	40042	300	0	0	0	0	0	3329	40028	16	16	25	161424	100	81366	80000	100	80000	80000	500	1839712	643339	0	40021	40043	40043	19959	3	20001	160100	200	80000	80000	200	160000	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80000	0	2	80000	2	42	0	5110	1	16	1	1	40039	80000	80000	100	40043	40043	40044	40046	40044
160204	40042	300	0	0	0	3	0	2222	40028	16	16	25	161804	100	81347	80000	100	80000	80000	500	1839712	644265	0	40021	40043	40042	19959	3	20000	160100	200	80000	80000	200	160000	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	2	80002	0	42	0	5110	1	16	1	1	40040	80000	80000	100	40044	40043	40043	40044	40044
160204	40042	300	0	0	0	0	1	4382	40028	0	16	25	163238	100	81468	80000	100	80000	80000	500	1839712	650866	0	40021	40042	40042	19959	3	20001	160100	200	80000	80000	200	160000	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	2	80000	2	0	0	5110	1	16	1	1	40039	80000	80000	100	40044	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	22	37	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160026	40042	300	0	0	0	0	3019	40028	16	16	0	25	163892	10	83656	80000	10	80000	80000	50	1839712	646359	1	40021	40042	40043	19982	3	20023	160234	20	80000	80000	20	160000	160000	40447	40451	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80000	1	6	80000	2	0	5020	13	16	12	9	40039	80000	80000	10	40043	40043	40043	40044	40043
160024	40042	300	0	0	0	0	3019	40027	16	16	0	25	163036	10	83352	80000	10	80000	80000	50	1839712	647154	1	40021	40042	40042	19982	3	20022	160010	20	80000	80000	20	160000	160000	40049	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	0	80002	2	34	5020	11	16	10	10	40039	80000	80000	10	40043	40043	40043	40043	40050
160024	40042	300	0	0	3	1	3567	40027	16	16	0	25	163029	10	82119	80000	10	80000	80108	50	1839736	650756	0	40024	40043	40043	19982	3	20023	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	5	80002	0	34	5020	12	16	17	11	40046	80000	80000	10	40044	40044	40043	40043	40050
160024	40042	299	0	0	3	0	3019	40028	16	16	0	25	163055	10	82384	80000	10	80000	80000	50	1839712	646364	0	40021	40043	40049	19985	3	20022	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80002	0	8	80000	2	0	5020	13	16	13	16	40039	80000	80000	10	40043	40054	40043	40050	40043
160024	40049	300	0	0	6	0	3649	40028	0	16	0	25	164180	10	82490	80000	10	80000	80000	50	1839712	649058	0	40021	40042	40042	19982	3	20022	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80000	0	2	80000	2	34	5020	11	16	13	11	40040	80000	80000	10	40043	40043	40043	40043	40043
160024	40043	300	0	0	3	0	3649	40028	0	0	1	25	163029	10	82119	80000	10	80000	80000	50	1839712	647711	0	40021	40049	40048	19984	3	20028	160010	20	80000	80000	20	160000	160000	40042	40048	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80002	0	0	80002	0	0	5020	13	16	14	13	40039	80000	80000	10	40043	40043	40044	40050	40044
160024	40043	300	0	0	3	0	3656	40027	16	16	0	25	162401	10	82160	80000	10	80000	80000	50	1839712	650948	1	40021	40042	40042	19982	3	20022	160010	20	80000	80000	20	160000	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	8	80000	2	34	5020	12	16	12	12	40039	80000	80000	10	40044	40043	40043	40044	40043
160024	40048	300	0	0	0	1	1365	40027	16	16	0	25	163036	10	83019	80000	10	80000	80000	50	1839832	646364	0	40021	40043	40043	19982	3	20023	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	5	80000	2	34	5020	12	16	12	12	40039	80000	80000	10	40044	40043	40043	40043	40043
160024	40042	300	0	0	3	1	3603	40027	16	16	0	25	163029	10	82119	80000	10	80000	80000	50	1839832	649051	0	40024	40043	40042	19982	3	20023	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	8	80002	0	34	5020	13	16	10	13	40045	80000	80000	10	40049	40044	40043	40043	40050
160024	40042	299	0	0	3	0	3656	40027	16	16	0	25	163027	10	83019	80000	10	80000	80000	50	1839712	650958	1	40021	40042	40043	19982	3	20028	160010	20	80000	80000	20	160000	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80000	0	0	80002	0	34	5020	12	16	14	12	40046	80000	80000	10	40043	40044	40247	40243	40050

STP (signed offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations