Firestorm: STR (D) measurements

Code:

  str d0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	551	4	0	0	0	0	3	1	0	543	16	16	0	25	1000	1000	1000	22832	1	526	542	542	355	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	5	1002	2	34	0	0	73	1	16	1	1	539	1000	543	543	543	555	552
1004	551	4	0	0	0	0	3	0	0	535	16	16	0	25	1000	1000	1000	22424	1	517	551	542	363	3	400	1000	1000	2000	550	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	8	1002	2	34	0	0	73	1	16	1	1	548	1000	543	552	552	543	543
1004	542	4	0	0	0	0	3	0	0	544	16	16	6	25	1000	1000	1000	22836	1	524	558	553	374	3	410	1000	1000	2000	561	559	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	2	1002	2	34	0	0	73	1	16	1	1	539	1000	560	553	552	550	561
1004	558	4	1	1	1	0	18	1	1	537	16	16	0	25	1000	1000	1000	22424	1	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1017	16	36	0	1	1016	0	0	18	1002	16	36	14	0	73	1	16	1	1	548	1000	551	552	543	543	543
1004	542	4	0	0	0	0	3	0	0	638	16	16	0	25	1000	1000	1000	22424	1	517	542	550	355	3	400	1000	1000	2000	542	551	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	8	1002	2	34	0	0	73	1	16	1	1	548	1000	543	543	543	543	552
1004	551	4	0	0	0	0	3	1	0	544	16	16	4	25	1000	1000	1000	22908	1	526	558	552	373	3	410	1000	1000	2000	560	559	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	2	1002	2	34	0	0	73	1	16	1	1	539	1000	543	543	543	550	551
1004	550	4	0	0	0	0	3	0	0	546	16	16	0	25	1000	1000	1000	22424	1	517	549	542	363	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	2	1002	2	34	0	0	73	1	16	1	1	539	1000	558	559	559	553	554
1004	553	4	1	0	0	1	21	0	1	544	16	16	0	25	1000	1000	1000	22424	1	517	542	551	355	3	409	1000	1000	2000	542	549	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	2	1002	2	34	0	0	73	1	16	1	1	539	1000	559	554	553	551	561
1004	561	4	1	0	0	1	19	0	1	536	16	16	0	25	1000	1000	1000	22424	1	517	549	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	0	0	1002	0	0	2	1002	2	34	0	0	73	1	16	1	1	547	1000	553	553	552	561	562
1004	559	4	1	1	0	1	20	0	1	535	16	16	0	25	1000	1000	1000	22424	1	517	550	542	362	3	400	1000	1000	2000	549	542	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	0	19	1002	16	36	14	0	73	1	16	1	1	556	1000	551	543	543	543	543

Count: 8

Code:

  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40053	300	0	0	0	0	0	0	18	0	0	1	40037	16	16	5	25	80100	100	80000	100	80000	500	1840292	40028	40042	40051	29953	3	30009	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	0	8	80002	2	36	14	1	5110	1	16	1	1	40049	80000	100	40051	40059	40051	40060	40059
80204	40059	300	1	1	1	0	0	0	0	1	0	0	40035	16	16	2	25	80100	100	80000	100	80000	500	1839424	40015	40049	40042	29955	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	1	0	2	80002	0	34	0	0	5110	1	16	1	1	40039	80000	100	40043	40043	40043	40041	40041
80204	40042	300	0	0	0	0	0	0	3	0	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	40027	40042	40042	29955	3	30008	80100	200	80000	200	160000	40042	40051	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	0	2	80002	2	36	14	1	5110	1	16	1	1	40049	80000	100	40051	40060	40053	40059	40061
80204	40047	300	1	1	0	0	0	0	3	0	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839424	40015	40042	40042	29953	3	30000	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	0	0	5	80002	2	34	0	0	5110	1	16	1	1	40039	80000	100	40041	40051	40043	40051	40041
80204	40042	300	0	0	0	0	0	0	0	1	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839784	40017	40042	40051	29964	3	29998	80100	200	80000	200	160000	40042	40051	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	0	0	80002	2	34	0	0	5130	1	16	1	1	40155	80000	100	40041	40043	40050	40041	40041
80204	40182	299	0	1	1	0	1	30	20	1	0	1	40043	16	0	0	25	80100	100	80000	100	80000	500	1840244	40025	40043	40042	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80000	1	0	2	80002	0	34	0	0	5110	1	16	1	1	40039	80000	100	40043	40051	40043	40041	40043
80204	40051	300	0	0	0	0	0	15	3	1	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	40033	40051	40051	29963	3	29998	80100	200	80000	200	160000	40050	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	1	0	0	80002	0	34	0	0	5110	1	16	1	1	40037	80000	100	40043	40043	40043	40043	40043
80204	40050	300	0	0	0	0	0	0	14	1	0	1	40045	16	16	4	25	80100	100	80000	100	80000	500	1840341	40015	40040	40042	29953	3	30007	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	80002	0	0	0	80002	2	34	0	4	5110	1	16	1	1	40039	80000	100	40043	40043	40043	40043	40043
80204	40049	300	0	0	0	0	0	0	6	1	0	0	40027	0	0	0	25	80100	100	80000	100	80000	500	1839832	40018	40042	40051	29953	3	30000	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80000	0	0	2	80000	2	0	0	0	5110	1	16	1	1	40048	80000	100	40043	40043	40041	40043	40041
80204	40042	300	0	0	0	0	0	0	9	0	0	0	40036	0	16	0	25	80100	100	80000	100	80000	500	1839856	40031	40047	40048	29971	3	30005	80100	200	80000	200	160000	40059	40058	1	1	80201	100	99	100	100	80000	80000	100	80016	14	36	0	80016	0	0	20	80002	16	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40051	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40053	300	1	1	1	1	0	18	0	0	1	40045	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	40015	40042	40042	29977	3	30020	80010	20	80000	20	160000	40051	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80000	0	0	0	80000	2	34	0	0	5020	0	0	5	16	0	3	5	40037	80000	10	40043	40043	40041	40043	40041
80024	40042	300	0	0	0	0	0	3	1	0	0	40037	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40042	40051	29975	3	30022	80010	20	80000	20	160000	40040	40051	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80002	0	0	2	80000	2	34	0	0	5020	0	0	3	16	0	3	5	40039	80000	10	40043	40043	40041	40041	40043
80024	40040	299	0	0	0	0	0	3	0	0	0	40036	16	16	0	25	80010	10	80000	10	80000	50	1840268	0	40026	40058	40058	29994	3	30027	80010	20	80000	20	160000	40058	40058	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	1	0	0	80002	2	34	0	0	5020	0	0	5	16	0	5	5	40039	80000	10	40041	40043	40041	40041	40043
80024	40042	300	0	0	0	0	0	9	0	0	0	40044	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40042	40042	29977	3	30020	80010	20	80000	20	160000	40042	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80002	0	0	2	80002	2	34	0	0	5020	0	0	3	16	0	5	3	40037	80000	10	40041	40041	40043	40051	40043
80024	40121	300	0	0	0	0	0	3	1	0	0	40038	16	16	0	25	80010	10	80000	10	80000	50	1839808	0	40017	40040	40040	29975	3	30020	80010	20	80000	20	160000	40049	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80002	0	0	2	80002	2	34	0	0	5020	0	0	5	16	0	3	5	40037	80000	10	40043	40043	40043	40043	40043
80024	40040	300	0	0	0	0	6	3	0	0	0	40044	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40040	40042	29977	3	30030	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80060	0	34	0	80000	0	0	2	80002	0	34	0	0	5020	0	0	5	16	0	5	5	40039	80000	10	40043	40041	40041	40041	40050
80025	40040	300	0	0	0	0	0	3	0	0	0	40043	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40047	40058	29992	3	30031	80010	20	80000	20	160000	40059	40061	1	1	80021	10	9	10	10	80000	80000	10	80016	15	36	2	80016	0	0	53	80002	0	0	0	0	5020	0	0	5	16	0	5	4	40037	80000	10	40051	40043	40041	40041	40052
80024	40042	300	0	0	0	0	0	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40024	40051	40040	29985	20	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80002	0	0	2	80002	2	34	0	0	5020	0	0	3	16	0	5	5	40048	80000	10	40043	40041	40043	40043	40043
80024	40051	299	0	0	0	0	0	9	0	0	0	40582	0	0	0	25	80010	10	80000	10	80000	50	1839424	0	40015	40042	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80002	0	0	2	80000	2	34	0	0	5020	0	0	3	16	0	3	5	40037	80000	10	40043	40052	40043	40052	40041
80024	40040	300	0	0	0	0	81	9	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	80000	0	0	0	80000	2	34	0	0	5020	0	0	5	16	0	5	3	40037	80000	10	40043	40041	40043	40043	40043

STR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations