Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STR (D)

Test 1: uops

Code:

  str d0, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)030508090b1f223a3f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
1005551400003105431616025100010001000228321526542542355340810001000200054254211100110001000100003400100200510022340073116115391000543543543555552
1004551400003005351616025100010001000224241517551542363340010001000200055054211100110001000100003400100200810022340073116115481000543552552543543
1004542400003005441616625100010001000228361524558553374341010001000200056155911100110001000100003400100200210022340073116115391000560553552550561
100455841110181153716160251000100010002242415175425423553400100010002000542542111001100010001017163601101600181002163614073116115481000551552543543543
1004542400003006381616025100010001000224241517542550355340010001000200054255111100110001000100003400100200810022340073116115481000543543543543552
1004551400003105441616425100010001000229081526558552373341010001000200056055911100110001000100003400100200210022340073116115391000543543543550551
1004550400003005461616025100010001000224241517549542363340010001000200054254211100110001000100003400100200210022340073116115391000558559559553554
10045534100121015441616025100010001000224241517542551355340910001000200054254911100110001000100003400100200210022340073116115391000559554553551561
10045614100119015361616025100010001000224241517549542355340010001000200054254211100110001000100003400100200210022340073116115471000553553552561562
100455941101200153516160251000100010002242415175505423623400100010002000549542111001100010001014143600101600191002163614073116115561000551543543543543

Test 2: throughput

Count: 8

Code:

  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0305080b18191e1f22233a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
802054005330000000018001400371616525801001008000010080000500184029240028400424005129953330009801002008000020016000040042400401180201100991001008000080000100800000340800020088000223614151101161140049800001004005140059400514006040059
8020440059300111000010040035161622580100100800001008000050018394244001540049400422995532999880100200800002001600004004240042118020110099100100800008000010080000034080002102800020340051101161140039800001004004340043400434004140041
8020440042300000000300040027016025801001008000010080000500183942440027400424004229955330008801002008000020016000040042400511180201100991001008000080000100800000340800000028000223614151101161140049800001004005140060400534005940061
802044004730011000030004002716002580100100800001008000050018394244001540042400422995333000080100200800002001600004004240040118020110099100100800008000010080000034080000005800022340051101161140039800001004004140051400434005140041
802044004230000000001004002716160258010010080000100800005001839784400174004240051299643299988010020080000200160000400424005111802011009910010080000800001008000000080002000800022340051301161140155800001004004140043400504004140041
80204401822990110130201014004316002580100100800001008000050018402444002540043400422995333000080100200800002001600004004240042118020110099100100800008000010080000034080000102800020340051101161140039800001004004340051400434004140043
80204400513000000015310040027161602580100100800001008000050018394244003340051400512996332999880100200800002001600004005040042118020110099100100800008000010080000034080002100800020340051101161140037800001004004340043400434004340043
80204400503000000001410140045161642580100100800001008000050018403414001540040400422995333000780100200800002001600004004240040118020110099100100800008000010080000034080002000800022340451101161140039800001004004340043400434004340043
802044004930000000061004002700025801001008000010080000500183983240018400424005129953330000801002008000020016000040042400401180201100991001008000080000100800000008000000280000200051101161140048800001004004340043400414004340041
80204400423000000009000400360160258010010080000100800005001839856400314004740048299713300058010020080000200160000400594005811802011009910010080000800001008001614360800160020800021600051101161140039800001004004340051400434004340043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030508090b1e1f22233a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd0d2d5d6daddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
800254005330011110180014004516160258001010800001080000501839424040015400424004229977330020800102080000201600004005140040118002110910108000080000108000003408000000080000234005020005160354003780000104004340043400414004340041
8002440042300000003100400370160258001010800001080000501839424040017400424005129975330022800102080000201600004004040051118002110910108000080000108000003408000200280000234005020003160354003980000104004340043400414004140043
8002440040299000003000400361616025800101080000108000050184026804002640058400582999433002780010208000020160000400584005811800211091010800008000010800000008000210080002234005020005160554003980000104004140043400414004140043
8002440042300000009000400440160258001010800001080000501839424040017400424004229977330020800102080000201600004004240049118002110910108000080000108000003408000200280002234005020003160534003780000104004140041400434005140043
80024401213000000031004003816160258001010800001080000501839808040017400404004029975330020800102080000201600004004940049118002110910108000080000108000003408000200280002234005020005160354003780000104004340043400434004340043
80024400403000000630004004416160258001010800001080000501839424040017400404004229977330030800102080000201600004004240040118002110910108000080000108006003408000000280002034005020005160554003980000104004340041400414004140050
80025400403000000030004004316002580010108000010800005018394240400174004740058299923300318001020800002016000040059400611180021109101080000800001080016153628001600538000200005020005160544003780000104005140043400414004140052
800244004230000000000040027161602580010108000010800005018393520400244005140040299852030020800102080000201600004004240042118002110910108000080000108000003408000200280002234005020003160554004880000104004340041400434004340043
800244005129900000900040582000258001010800001080000501839424040015400424004229977330022800102080000201600004004240042118002110910108000080000108000003408000200280000234005020003160354003780000104004340052400434005240041
800244004030000008190004002716160258001010800001080000501839352040017400424004229977330022800102080000201600004004040042118002110910108000080000108000003408000000080000234005020005160534003780000104004340041400434004340043