Firestorm: STR (Q) measurements

Code:

  str q0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	0	0	0	6	18	1	0	1	539	16	16	7	25	1000	1000	1000	23028	527	564	554	365	3	409	1000	1000	2000	555	553	1	1	1001	1000	1000	1016	15	44	0	1	1016	0	0	16	1002	16	44	14	0	73	1	16	1	1	550	1000	555	555	555	553	553
1004	552	4	1	1	1	0	0	19	0	0	1	539	16	16	6	25	1000	1000	1000	22933	528	552	556	364	3	412	1000	1000	2000	551	554	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	1	18	1002	16	44	14	1	73	1	16	1	1	551	1000	555	555	555	555	555
1004	554	4	1	1	0	1	0	17	0	0	1	549	16	16	2	25	1000	1000	1000	23028	528	552	554	365	3	412	1000	1000	2000	552	554	1	1	1001	1000	1000	1015	15	44	0	1	1016	0	0	18	1002	16	44	14	0	73	1	16	1	1	560	1000	553	552	564	555	555
1004	554	4	1	1	1	1	0	18	0	0	1	539	16	15	0	25	1000	1000	1000	23004	527	563	554	365	3	412	1000	1000	2000	552	554	1	1	1001	1000	1000	1014	14	44	0	0	1016	0	1	18	1002	16	44	14	1	73	1	16	1	1	551	1000	552	564	555	555	555
1004	554	4	1	0	0	0	0	20	0	0	1	539	16	16	4	25	1000	1000	1000	23004	529	554	564	367	3	412	1000	1000	2000	554	552	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	1	16	1002	16	44	14	0	73	1	16	1	1	551	1000	555	555	555	555	555
1004	552	4	1	0	0	0	0	18	0	0	1	539	16	15	0	25	1000	1000	1000	23004	529	554	552	367	3	422	1000	1000	2000	554	552	1	1	1001	1000	1000	1015	15	42	0	0	1016	0	1	16	1002	16	44	14	0	73	1	16	1	1	551	1000	553	564	555	555	555
1004	554	4	1	1	1	0	0	19	1	0	1	536	16	16	1	25	1000	1000	1000	23004	538	554	551	367	3	412	1000	1000	2000	554	552	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	0	17	1002	16	44	14	2	73	1	16	1	1	551	1000	555	555	555	555	554
1004	552	4	1	0	1	1	0	18	0	0	1	539	16	15	0	25	1000	1000	1000	23004	528	552	554	364	3	412	1000	1000	2000	551	554	1	1	1001	1000	1000	1015	15	44	0	0	1016	0	0	16	1002	16	44	14	0	73	1	16	1	1	549	1000	555	555	554	553	553
1004	563	4	1	0	0	1	0	19	0	0	1	539	16	16	0	25	1000	1000	1000	23028	539	554	552	367	3	410	1000	1000	2000	554	554	1	1	1001	1000	1000	1015	14	44	0	1	1016	0	1	18	1002	16	44	14	1	73	1	16	1	1	551	1000	553	564	556	555	555
1004	554	4	1	0	1	0	0	17	1	0	1	539	16	16	2	25	1000	1000	1000	22908	529	551	554	366	3	412	1000	1000	2000	553	554	1	1	1001	1000	1000	1014	14	44	0	1	1016	0	1	16	1002	16	44	14	1	73	1	16	1	1	549	1000	555	554	552	553	564

Count: 8

Code:

  str q0, [x6]
  str q0, [x6]
  str q0, [x6]
  str q0, [x6]
  str q0, [x6]
  str q0, [x6]
  str q0, [x6]
  str q0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	300	0	0	0	3	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839472	40017	40043	40043	29955	3	30000	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	42	80002	0	2	80002	2	0	0	5110	3	16	3	3	40037	80000	100	40043	40043	40043	40043	40043
80204	40042	300	0	0	0	0	1	0	40028	16	0	0	25	80100	100	80000	100	80000	500	1839448	40015	40042	40042	29956	3	29998	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	0	80002	2	0	0	5110	2	16	3	3	40039	80000	100	40041	40055	40043	40041	40043
80204	40042	300	0	0	0	3	1	0	40027	16	0	1	25	80100	100	80000	100	80000	500	1839352	40017	40040	40040	29953	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	0	80002	2	0	0	5110	2	16	3	3	40051	80000	100	40051	40043	40043	40041	40043
80204	40040	300	0	0	0	3	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40042	40043	29955	3	30001	80100	200	80000	200	160000	40042	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	80000	0	0	80002	2	42	0	5110	3	16	3	3	40040	80000	100	40041	40044	40041	40043	40041
80204	40042	300	0	0	0	3	0	0	40025	16	0	1	25	80100	100	80000	100	80000	500	1839448	40017	40042	40042	29953	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	8	80000	2	42	0	5110	3	16	2	3	40039	80000	100	40043	40043	40043	40043	40041
80204	40042	300	0	0	0	3	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839448	40017	40042	40042	29967	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	80000	1	0	80002	0	0	0	5110	3	16	3	3	40037	80000	100	40044	40041	40043	40044	40043
80204	40043	300	0	0	6	3	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839472	40017	40040	40040	29956	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	80002	0	2	80012	2	42	0	5110	3	16	3	2	40039	80000	100	40041	40043	40043	40043	40043
80204	40042	300	0	0	0	3	1	0	40027	0	0	1	25	80100	100	80000	100	80000	500	1839472	40018	40040	40043	29955	3	30001	80100	200	80000	200	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	42	80000	0	2	80002	2	42	0	5110	3	16	3	3	40040	80000	100	40043	40055	40043	40041	40043
80204	40040	300	1	0	6	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839448	40015	40042	40042	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	80002	0	2	80000	2	42	0	5110	3	16	3	3	40040	80000	100	40043	40044	40043	40043	40044
80204	40042	300	0	0	0	3	0	0	40027	16	0	1	25	80100	100	80000	100	80000	500	1839448	40015	40040	40040	29956	3	30001	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	0	80002	2	0	0	5110	3	16	2	3	40040	80000	100	40044	40044	40043	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40052	301	1	0	0	0	0	14	1	0	1	40044	16	0	7	25	80010	10	80000	10	80000	50	1839836	1	40027	40061	40051	29986	3	30032	80010	20	80000	20	160000	40052	40058	1	1	80021	10	9	10	10	80000	80000	10	80015	14	36	0	2	80014	0	1	19	80002	14	36	14	0	5020	1	16	1	1	40056	80000	10	40048	40059	40051	40060	40048
80024	40057	300	1	0	0	1	0	20	0	0	1	40037	16	16	7	40	80010	10	80000	10	80000	50	1839860	1	40027	40061	40047	29986	3	30038	80010	20	80000	20	160000	40058	40060	1	1	80021	10	9	10	10	80000	80000	10	80014	15	36	94	0	80196	1	1	19	80062	16	36	14	1	5020	1	16	1	1	40044	80000	10	40060	40048	40048	40060	40059
80024	40047	300	1	1	0	1	0	17	1	0	1	40037	16	16	9	25	80010	10	80000	10	80000	50	1839908	1	40022	40060	40052	29982	3	30028	80010	20	80000	20	160000	40048	40047	1	1	80021	10	9	10	10	80000	80000	10	80014	15	0	0	1	80016	0	1	14	80002	16	36	14	2	5020	2	16	1	1	40044	80000	10	40048	40060	40048	40059	40052
80024	40058	300	1	1	1	1	0	19	1	0	1	40032	0	0	0	25	80010	10	80000	10	80000	50	1839860	1	40036	40047	40058	29994	3	30027	80010	20	80000	20	160000	40052	40059	1	1	80021	10	9	10	10	80000	80000	10	80014	14	0	0	1	80014	0	0	20	80002	16	36	14	1	5020	1	16	1	1	40049	80000	10	40049	40053	40062	40059	40062
80024	40058	300	1	1	1	1	0	19	0	0	1	40044	16	16	1	25	80010	10	80000	10	80000	50	1839692	1	40022	40047	40052	29988	3	30028	80010	20	80000	20	160000	40059	40047	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	1	80014	0	0	21	80000	16	0	14	1	5020	1	16	1	1	40050	80000	10	40049	40053	40062	40059	40062
80024	40058	300	1	1	0	1	0	14	1	0	1	40032	0	16	2	25	80010	10	80000	10	80000	50	1839692	1	40033	40051	40047	29987	3	30027	80010	20	80000	20	160000	40059	40047	1	1	80021	10	9	10	10	80000	80000	10	80014	16	0	0	0	80016	0	1	16	80002	14	0	14	1	5020	1	16	1	1	40048	80000	10	40059	40052	40060	40054	40060
80024	40058	300	1	0	1	1	0	20	1	0	1	40033	16	16	0	25	80010	10	80000	10	80000	50	1839908	1	40028	40059	40047	29985	3	30039	80010	20	80000	20	160000	40059	40059	1	1	80021	10	9	10	10	80000	80000	10	80015	16	0	0	1	80016	0	1	17	80002	14	36	14	1	5020	1	16	1	1	40045	80000	10	40048	40208	40053	40048	40053
80024	40050	300	1	1	1	1	0	19	1	0	1	40032	16	16	2	25	80010	10	80000	10	80000	50	1839692	1	40033	40052	40059	29987	3	30027	80010	20	80000	20	160000	40060	40047	1	1	80021	10	9	10	10	80000	80000	10	80014	14	0	0	1	80016	0	1	20	80000	16	0	14	0	5020	1	16	1	1	40057	80000	10	40060	40061	40059	40052	40048
80024	40047	300	1	1	1	1	0	15	1	0	1	40032	16	16	2	25	80010	10	80000	10	80000	50	1840268	1	40033	40051	40052	29987	3	30027	80010	20	80000	20	160000	40059	40059	1	1	80021	10	9	10	10	80000	80000	10	80014	14	0	0	0	80016	0	1	14	80000	16	36	14	1	5020	1	16	1	1	40044	80000	10	40053	40049	40053	40048	40048
80024	40047	300	1	0	0	0	0	14	0	0	1	40044	16	0	5	25	80010	10	80000	10	80000	50	1840221	1	40022	40058	40060	29982	3	30039	80010	20	80000	20	160000	40059	40047	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	1	80014	1	1	18	80002	16	36	14	2	5020	1	16	1	1	40048	80000	10	40048	40048	40048	40054	40060

STR (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations