Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STR (S)

Test 1: uops

Code:

  str s0, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)030508090b1e1f22233a3f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
10055474111161910154416162251000100010002324405275615473623405100010002000558553111001100010001014143601101601191002163614173216335491000559548548553552
1004550411110210015431616025100010001000226920526558547373341110001000200056055811100110001000101514000101601201000163614173316335441000554553551548559
10045474111101900153816160251000100010002269205345525473603417100010002000558561111001100010001014143600101601181002143614073316335491000548560560553562
10045474111101400154400625100010001000233160526558552363341010001000200054755911100110001000101515000101600181002163614173316335441000548548560548553
1004552410100141015321601251000100010002293205345595603713419100010002000558547111001100010001014143600101401141002163614073316335441000559548554553559
10045484110012201015371616125100010001000232200526547547363341010001000200055054711100110001000101415360010140118100216014273316335551000559559559548553
1004547411010190015441616725100010001000232680526559552373341110001000200056054711100110001000101616360010160116100014014273316335561000558560548553561
1004561411010180015320166251000100010002322005275605473633410100010002000550559111001100010001015143600101402171002163614173216235441000559559553554549
10045584101001900154416168251000100010002269205225475523733405100010002000560558111001100010001016143600101400141000163614073316335441000553548548549553
100454741001018101543005251000100010002324405265595523733411100010002000560558111001100010001014143600101600161002163614073316335441000553553552561548

Test 2: throughput

Count: 8

Code:

  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080b18191e1f2223243a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)c2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
802054004230000000031000400270160258010010080000100800005001839808040017400514004229963330000801002008000020016000040042400501180201100991001008000080000100800000340080002002800022340000511011611400370800001004004340041400414004340043
8020440042300000010600004003516160258010010080000100800005001839424040137400504004229955330000801002008000020016000040042406051180201100991001008000080000100800000340080002409800002340000511011611400460800001004005040041401924033740043
80204400403000001015910004002716160258010010080000100800005001839424040017400424004029953330000801002008000020016000040042400421180201100991001008000080000100800000340080002008800020340000511011611400390800001004005140043400434004340043
802044004229900000001000400270160258010010080000100800005001839424040017400404004229955330000801002008000020016000040042400421180201100991001008000080000100800000380080002002800002340000511011611400390800001004004340041400514004140041
802044004030000000000000400271600258010010080000100800005001839352040017400514005029953329998801002008000020016000040051400401180201100991001008000080000100800000340080000202800022340000511011611400390800001004005240041400434004340043
80204400423000000000000040036161602580100100800001008000050018393520400174004240040299553301248010020080000200160000400424005111802011009910010080000800001008000003400800026200800002340000511011611400370800001004004140043400414004140043
802044004230000000030000400270160145801001008000010080000500183942414001740050400422995533000080100200800002001600004004040042118020110099100100800008000010080000034008000210280002200000511011611400370800001004004340043400414004340041
802044004229900000031000400271600258010010080000100800005001839808040017400404004029963330000801002008000020016000040040400421180201100991001008000080000100800000340080002202800022340000511011611400480800001004004140043400434004340043
8020440051300000000300004002516160258010010080000100800005001839424040026400424004229955329998801002008000020016000040042400421180201100991001008000080000100800000340080002202800002340000511011611400390800001004005040041400434004140043
802044004230000000000000400271600258016010080000100800005001839352040017400504004229955330000801002008000020016000040042400421180201100991001008000080000100800000340080000208800020340000511011611400390800001004004140043400434004340041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030408090b18191e1f223f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)c2cfitlb miss (d4)d5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)gpr retires (ef)f5f6f7f8fd
8002540043300101000030400280160258001010800001080432501839448040017400404004229977330022800102080000201600004004340042118002110910108000080000108000004200800632038000224205020016161810400390080000104004340055400434004340047
8002440043300101000031400280161258001010800001080000501839448140017400424004029977330022800102080000201600004005440042118002110910108000080000108000004200800002505800022005021117161617400370080000104004340044400414004340043
8002440042300101000331400281616125800101080000108000050183944814001740042400422997833002280010208000020160000400404004211800211091010800008000010800000420080002108800022005021116161417403960080000104004340041400434005540043
8002440040300101000031400250161258001010800001080000601839448140018400424004229978330022800102080000201600004004240042118002110910108000080000108000004200800020028000224205021115161416400390080000104004340043400414004440044
800244004230010100003140027161686258001010801201080000501839448140017404594018129977330020800102280000201600004018940042318002110910108000080000108000000008006224016688000224205021116161616400390080000104004340043400444004140045
8002440042299101000031400281616025800101080000108000050183947214001840043400432997733002280010208000020160000400434004311800211091010800008000010800000420080002102800022420502111716816400390080000104059840043400434004340044
80024400423001010006314002816161258001010800001080000501839448140018400424004029978330022800102080000201600004004240042118002110910108000080000108000004200800020017800022005021116161416400390080000104004140041400444004440044
800244004230010100003140027000258001010800001080000501839352140017400404004229977330020800102080000201600004004040042118002110910108000080000108000000008000200880000200502119161714400370080000104004340041400414004340043
800244004030010100003140025161602580010108000010800005018393521400184004340042299783300228001020800002016000040040400421180021109101080000800001080000042008036300239180002242050211816178400370080000104004340458400434004340043
8002440040300101000931400270002580010108000010800005018393521401374004240042299781630022800102080000201600004004040042118002110910108000080000108000024200800027017800022420502111716917400390080000104004140044400414004340043