Firestorm: STR (S) measurements

Code:

  str s0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	547	4	1	1	1	1	6	19	1	0	1	544	16	16	2	25	1000	1000	1000	23244	0	527	561	547	362	3	405	1000	1000	2000	558	553	1	1	1001	1000	1000	1014	14	36	0	1	1016	0	1	19	1002	16	36	14	1	73	2	16	3	3	549	1000	559	548	548	553	552
1004	550	4	1	1	1	1	0	21	0	0	1	543	16	16	0	25	1000	1000	1000	22692	0	526	558	547	373	3	411	1000	1000	2000	560	558	1	1	1001	1000	1000	1015	14	0	0	0	1016	0	1	20	1000	16	36	14	1	73	3	16	3	3	544	1000	554	553	551	548	559
1004	547	4	1	1	1	1	0	19	0	0	1	538	16	16	0	25	1000	1000	1000	22692	0	534	552	547	360	3	417	1000	1000	2000	558	561	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	1	18	1002	14	36	14	0	73	3	16	3	3	549	1000	548	560	560	553	562
1004	547	4	1	1	1	1	0	14	0	0	1	544	0	0	6	25	1000	1000	1000	23316	0	526	558	552	363	3	410	1000	1000	2000	547	559	1	1	1001	1000	1000	1015	15	0	0	0	1016	0	0	18	1002	16	36	14	1	73	3	16	3	3	544	1000	548	548	560	548	553
1004	552	4	1	0	1	0	0	14	1	0	1	532	16	0	1	25	1000	1000	1000	22932	0	534	559	560	371	3	419	1000	1000	2000	558	547	1	1	1001	1000	1000	1014	14	36	0	0	1014	0	1	14	1002	16	36	14	0	73	3	16	3	3	544	1000	559	548	554	553	559
1004	548	4	1	1	0	0	12	20	1	0	1	537	16	16	1	25	1000	1000	1000	23220	0	526	547	547	363	3	410	1000	1000	2000	550	547	1	1	1001	1000	1000	1014	15	36	0	0	1014	0	1	18	1002	16	0	14	2	73	3	16	3	3	555	1000	559	559	559	548	553
1004	547	4	1	1	0	1	0	19	0	0	1	544	16	16	7	25	1000	1000	1000	23268	0	526	559	552	373	3	411	1000	1000	2000	560	547	1	1	1001	1000	1000	1016	16	36	0	0	1016	0	1	16	1000	14	0	14	2	73	3	16	3	3	556	1000	558	560	548	553	561
1004	561	4	1	1	0	1	0	18	0	0	1	532	0	16	6	25	1000	1000	1000	23220	0	527	560	547	363	3	410	1000	1000	2000	550	559	1	1	1001	1000	1000	1015	14	36	0	0	1014	0	2	17	1002	16	36	14	1	73	2	16	2	3	544	1000	559	559	553	554	549
1004	558	4	1	0	1	0	0	19	0	0	1	544	16	16	8	25	1000	1000	1000	22692	0	522	547	552	373	3	405	1000	1000	2000	560	558	1	1	1001	1000	1000	1016	14	36	0	0	1014	0	0	14	1000	16	36	14	0	73	3	16	3	3	544	1000	553	548	548	549	553
1004	547	4	1	0	0	1	0	18	1	0	1	543	0	0	5	25	1000	1000	1000	23244	0	526	559	552	373	3	411	1000	1000	2000	560	558	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	0	16	1002	16	36	14	0	73	3	16	3	3	544	1000	553	553	552	561	548

Count: 8

Code:

  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	0	0	0	3	1	0	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839808	0	40017	40051	40042	29963	3	30000	80100	200	80000	200	160000	40042	40050	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	0	0	0	5110	1	16	1	1	40037	0	80000	100	40043	40041	40041	40043	40043
80204	40042	300	0	0	0	0	1	0	6	0	0	0	0	40035	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	40137	40050	40042	29955	3	30000	80100	200	80000	200	160000	40042	40605	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	4	0	9	80000	2	34	0	0	0	0	5110	1	16	1	1	40046	0	80000	100	40050	40041	40192	40337	40043
80204	40040	300	0	0	0	1	0	15	9	1	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	40017	40042	40040	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	8	80002	0	34	0	0	0	0	5110	1	16	1	1	40039	0	80000	100	40051	40043	40043	40043	40043
80204	40042	299	0	0	0	0	0	0	0	1	0	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	0	40017	40040	40042	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	38	0	0	80002	0	0	2	80000	2	34	0	0	0	0	5110	1	16	1	1	40039	0	80000	100	40043	40041	40051	40041	40041
80204	40040	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839352	0	40017	40051	40050	29953	3	29998	80100	200	80000	200	160000	40051	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80000	2	0	2	80002	2	34	0	0	0	0	5110	1	16	1	1	40039	0	80000	100	40052	40041	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	0	0	0	0	0	40036	16	16	0	25	80100	100	80000	100	80000	500	1839352	0	40017	40042	40040	29955	3	30124	80100	200	80000	200	160000	40042	40051	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	62	0	0	80000	2	34	0	0	0	0	5110	1	16	1	1	40037	0	80000	100	40041	40043	40041	40041	40043
80204	40042	300	0	0	0	0	0	0	3	0	0	0	0	40027	0	16	0	145	80100	100	80000	100	80000	500	1839424	1	40017	40050	40042	29955	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	1	0	2	80002	2	0	0	0	0	0	5110	1	16	1	1	40037	0	80000	100	40043	40043	40041	40043	40041
80204	40042	299	0	0	0	0	0	0	3	1	0	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839808	0	40017	40040	40040	29963	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	2	0	2	80002	2	34	0	0	0	0	5110	1	16	1	1	40048	0	80000	100	40041	40043	40043	40043	40043
80204	40051	300	0	0	0	0	0	0	3	0	0	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	40026	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	2	0	2	80000	2	34	0	0	0	0	5110	1	16	1	1	40039	0	80000	100	40050	40041	40043	40041	40043
80204	40042	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	0	0	25	80160	100	80000	100	80000	500	1839352	0	40017	40050	40042	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80000	2	0	8	80002	0	34	0	0	0	0	5110	1	16	1	1	40039	0	80000	100	40041	40043	40043	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40043	300	1	0	1	0	0	0	0	3	0	40028	0	16	0	25	80010	10	80000	10	80432	50	1839448	0	40017	40040	40042	29977	3	30022	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80063	2	0	3	80002	2	42	0	5020	0	16	16	18	10	40039	0	0	80000	10	40043	40055	40043	40043	40047
80024	40043	300	1	0	1	0	0	0	0	3	1	40028	0	16	1	25	80010	10	80000	10	80000	50	1839448	1	40017	40042	40040	29977	3	30022	80010	20	80000	20	160000	40054	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80000	25	0	5	80002	2	0	0	5021	1	17	16	16	17	40037	0	0	80000	10	40043	40044	40041	40043	40043
80024	40042	300	1	0	1	0	0	0	3	3	1	40028	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	40017	40042	40042	29978	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	1	0	8	80002	2	0	0	5021	1	16	16	14	17	40396	0	0	80000	10	40043	40041	40043	40055	40043
80024	40040	300	1	0	1	0	0	0	0	3	1	40025	0	16	1	25	80010	10	80000	10	80000	60	1839448	1	40018	40042	40042	29978	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5021	1	15	16	14	16	40039	0	0	80000	10	40043	40043	40041	40044	40044
80024	40042	300	1	0	1	0	0	0	0	3	1	40027	16	16	86	25	80010	10	80120	10	80000	50	1839448	1	40017	40459	40181	29977	3	30020	80010	22	80000	20	160000	40189	40042	3	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80062	24	0	1668	80002	2	42	0	5021	1	16	16	16	16	40039	0	0	80000	10	40043	40043	40044	40041	40045
80024	40042	299	1	0	1	0	0	0	0	3	1	40028	16	16	0	25	80010	10	80000	10	80000	50	1839472	1	40018	40043	40043	29977	3	30022	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	1	0	2	80002	2	42	0	5021	1	17	16	8	16	40039	0	0	80000	10	40598	40043	40043	40043	40044
80024	40042	300	1	0	1	0	0	0	6	3	1	40028	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	40018	40042	40040	29978	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	17	80002	2	0	0	5021	1	16	16	14	16	40039	0	0	80000	10	40041	40041	40044	40044	40044
80024	40042	300	1	0	1	0	0	0	0	3	1	40027	0	0	0	25	80010	10	80000	10	80000	50	1839352	1	40017	40040	40042	29977	3	30020	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	8	80000	2	0	0	5021	1	9	16	17	14	40037	0	0	80000	10	40043	40041	40041	40043	40043
80024	40040	300	1	0	1	0	0	0	0	3	1	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40018	40043	40042	29978	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80363	0	0	2391	80002	2	42	0	5021	1	8	16	17	8	40037	0	0	80000	10	40043	40458	40043	40043	40043
80024	40040	300	1	0	1	0	0	0	9	3	1	40027	0	0	0	25	80010	10	80000	10	80000	50	1839352	1	40137	40042	40042	29978	16	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	2	42	0	0	80002	7	0	17	80002	2	42	0	5021	1	17	16	9	17	40039	0	0	80000	10	40041	40044	40041	40043	40043

STR (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations