Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
str d0, [x6], #0x10
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 23 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 7 | 1 | 1 | 1 | 0 | 15 | 11 | 36 | 0 | 0 | 0 | 5 | 12 | 1025 | 0 | 3 | 4 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1028 | 9 | 57 | 8 | 15 | 1010 | 0 | 1 | 0 | 12 | 13 | 1024 | 7 | 64 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 0 | 0 | 0 | 11 | 50 | 1 | 0 | 8 | 17 | 20 | 1025 | 21 | 1 | 1 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1062 | 9 | 57 | 7 | 45 | 1007 | 0 | 1 | 36 | 24 | 24 | 1036 | 7 | 52 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 2 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 2 | 0 | 1 | 0 | 11 | 0 | 0 | 0 | 0 | 2 | 0 | 1025 | 0 | 0 | 1 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1050 | 8 | 32 | 4 | 37 | 1013 | 0 | 0 | 0 | 0 | 14 | 1029 | 9 | 48 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 1 | 0 | 0 | 12 | 15 | 1 | 0 | 0 | 17 | 16 | 1025 | 16 | 4 | 3 | 4 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 7 | 65 | 4 | 43 | 1012 | 0 | 0 | 53 | 12 | 13 | 1048 | 7 | 48 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 3 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 0 | 0 | 0 | 11 | 4 | 1 | 0 | 0 | 15 | 0 | 1025 | 12 | 16 | 11 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1033 | 8 | 44 | 7 | 23 | 1012 | 0 | 0 | 30 | 16 | 20 | 1021 | 7 | 52 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 3 | 0 | 0 | 11 | 12 | 0 | 0 | 0 | 2 | 0 | 1025 | 0 | 0 | 0 | 5 | 33 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1020 | 7 | 65 | 11 | 36 | 1012 | 1 | 0 | 48 | 16 | 10 | 1059 | 7 | 40 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 1 | 0 | 6 | 11 | 40 | 1 | 0 | 0 | 20 | 16 | 1025 | 24 | 5 | 1 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1027 | 7 | 61 | 7 | 46 | 1011 | 0 | 1 | 36 | 0 | 24 | 1030 | 7 | 40 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 1 | 1 | 0 | 12 | 44 | 0 | 0 | 0 | 19 | 4 | 1025 | 8 | 9 | 0 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1007 | 8 | 44 | 5 | 18 | 1007 | 0 | 0 | 40 | 0 | 10 | 1046 | 7 | 44 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 0 | 1 | 0 | 10 | 12 | 0 | 0 | 0 | 2 | 4 | 1025 | 22 | 3 | 0 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1054 | 8 | 44 | 9 | 32 | 1015 | 0 | 0 | 40 | 0 | 11 | 1053 | 7 | 28 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 1 | 2 | 0 | 11 | 12 | 0 | 0 | 0 | 18 | 20 | 1025 | 30 | 0 | 0 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1034 | 8 | 48 | 9 | 36 | 1015 | 0 | 0 | 36 | 12 | 10 | 1036 | 7 | 44 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
str d0, [x6], #0x10
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10214 | 10040 | 75 | 1 | 0 | 1 | 10413 | 67 | 2304 | 1 | 1472 | 6 | 0 | 752 | 10025 | 2265 | 0 | 210 | 183 | 37 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522181 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12501 | 10 | 1658 | 1451 | 0 | 1526 | 11060 | 1440 | 0 | 2485 | 50 | 4716 | 12505 | 31 | 625 | 7 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 267 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 0 | 10473 | 53 | 2275 | 1 | 1448 | 4 | 0 | 976 | 10025 | 2260 | 0 | 224 | 198 | 35 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522017 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12479 | 17 | 1665 | 1429 | 0 | 1527 | 11002 | 1453 | 4 | 2485 | 50 | 4668 | 12514 | 29 | 746 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 326 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 2 | 0 | 0 | 10266 | 51 | 2319 | 1 | 1472 | 6 | 0 | 1188 | 10025 | 2224 | 0 | 197 | 208 | 38 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12505 | 8 | 1512 | 1410 | 0 | 1507 | 11056 | 1455 | 6 | 2468 | 50 | 4605 | 12511 | 31 | 713 | 7 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 160 | 3 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 1 | 10422 | 56 | 2354 | 1 | 1448 | 6 | 1 | 764 | 10025 | 2233 | 0 | 203 | 194 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522149 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12502 | 15 | 1663 | 1439 | 0 | 1450 | 11080 | 1463 | 4 | 2485 | 50 | 4553 | 12504 | 26 | 761 | 0 | 1 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 189 | 3 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 1 | 10341 | 84 | 2273 | 1 | 1416 | 2 | 0 | 840 | 10025 | 2227 | 0 | 193 | 208 | 25 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522163 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12489 | 9 | 1661 | 1459 | 0 | 1517 | 11016 | 1468 | 0 | 2496 | 50 | 4636 | 12504 | 28 | 732 | 7 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 339 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 1 | 10410 | 33 | 2308 | 1 | 1472 | 5 | 0 | 760 | 10025 | 2229 | 0 | 203 | 210 | 18 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522171 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12505 | 15 | 1622 | 1443 | 0 | 1518 | 11002 | 1439 | 4 | 2489 | 50 | 4621 | 12506 | 16 | 680 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 371 | 4 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 2 | 2 | 0 | 10248 | 42 | 2255 | 1 | 1608 | 6 | 0 | 1044 | 10025 | 2310 | 0 | 219 | 196 | 29 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522195 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12509 | 10 | 1716 | 1459 | 0 | 1511 | 11038 | 1446 | 4 | 2461 | 50 | 4637 | 12519 | 23 | 670 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 200 | 0 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 1 | 0 | 10299 | 60 | 2336 | 1 | 1688 | 8 | 0 | 968 | 10025 | 2246 | 0 | 213 | 229 | 31 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522195 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12520 | 8 | 1600 | 1451 | 0 | 1478 | 10979 | 1466 | 6 | 2493 | 50 | 4509 | 12499 | 28 | 762 | 0 | 1 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 236 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 76 | 2 | 0 | 0 | 10317 | 49 | 2319 | 1 | 1688 | 6 | 0 | 764 | 10025 | 2239 | 0 | 173 | 212 | 25 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522171 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12505 | 9 | 1676 | 1496 | 0 | 1454 | 11054 | 1478 | 0 | 2484 | 50 | 4679 | 12521 | 32 | 668 | 7 | 2 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 244 | 0 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 0 | 10452 | 52 | 2282 | 1 | 1680 | 7 | 0 | 956 | 10025 | 2231 | 0 | 244 | 220 | 19 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522147 | 468824 | 0 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12483 | 14 | 1679 | 1481 | 0 | 1520 | 11041 | 1452 | 0 | 2477 | 50 | 4615 | 12497 | 22 | 712 | 0 | 1 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 323 | 4 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10034 | 10040 | 75 | 2 | 0 | 0 | 0 | 0 | 10110 | 68 | 2305 | 1 | 1528 | 10 | 844 | 10025 | 2238 | 274 | 257 | 47 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521041 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12484 | 15 | 1685 | 1568 | 0 | 1569 | 10960 | 1395 | 8 | 2480 | 50 | 4608 | 12507 | 38 | 822 | 7 | 4 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 263 | 6 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 2 | 0 | 0 | 0 | 9882 | 76 | 2290 | 1 | 1544 | 11 | 936 | 10025 | 2236 | 258 | 251 | 40 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 0 | 10021 | 10192 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12483 | 9 | 1602 | 1531 | 0 | 1557 | 10938 | 1431 | 4 | 2477 | 50 | 4645 | 12509 | 42 | 695 | 7 | 0 | 640 | 3 | 16 | 3 | 2 | 10037 | 10000 | 230 | 5 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 2 | 0 | 2 | 0 | 10296 | 70 | 2267 | 1 | 1528 | 6 | 844 | 10025 | 2253 | 232 | 234 | 31 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521057 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 13 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12479 | 8 | 1602 | 1543 | 0 | 1563 | 10969 | 1426 | 2 | 2485 | 50 | 4636 | 12520 | 40 | 772 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 125 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 0 | 0 | 10167 | 72 | 2264 | 1 | 1664 | 6 | 804 | 10025 | 2260 | 234 | 209 | 34 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521057 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12484 | 7 | 1497 | 1521 | 0 | 1588 | 10963 | 1457 | 6 | 2464 | 50 | 6616 | 12511 | 42 | 727 | 7 | 0 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 219 | 2 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 2 | 0 | 0 | 0 | 0 | 9915 | 73 | 2293 | 1 | 1704 | 5 | 844 | 10025 | 2261 | 203 | 262 | 33 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521025 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12487 | 7 | 1579 | 1524 | 0 | 1575 | 10938 | 1432 | 0 | 2464 | 50 | 4618 | 12511 | 44 | 725 | 7 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 335 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 0 | 10119 | 56 | 2292 | 1 | 1496 | 4 | 724 | 10025 | 2215 | 241 | 210 | 43 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521057 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12475 | 7 | 1650 | 1571 | 0 | 1589 | 10962 | 1425 | 4 | 2484 | 50 | 4488 | 12514 | 39 | 627 | 7 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 264 | 4 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 0 | 10092 | 83 | 2305 | 1 | 1672 | 4 | 844 | 10025 | 2252 | 189 | 269 | 36 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12475 | 9 | 1659 | 1567 | 0 | 1592 | 10975 | 1428 | 2 | 2485 | 50 | 4610 | 12517 | 43 | 726 | 7 | 0 | 640 | 3 | 25 | 2 | 2 | 10037 | 10000 | 236 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 2 | 0 | 0 | 0 | 10224 | 67 | 2267 | 1 | 1704 | 2 | 732 | 10025 | 2240 | 187 | 218 | 53 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521041 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12484 | 9 | 1643 | 1528 | 0 | 1589 | 10923 | 1448 | 0 | 2492 | 50 | 4572 | 12523 | 38 | 704 | 7 | 2 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 394 | 5 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 0 | 0 | 0 | 9915 | 66 | 2302 | 1 | 1712 | 4 | 724 | 10025 | 2229 | 259 | 243 | 36 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521017 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12492 | 8 | 1581 | 1559 | 0 | 1581 | 10953 | 1460 | 0 | 2473 | 50 | 4585 | 12502 | 39 | 659 | 7 | 0 | 640 | 3 | 16 | 2 | 3 | 10037 | 10000 | 187 | 5 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 1 | 0 | 0 | 10164 | 66 | 2290 | 1 | 1640 | 6 | 808 | 10025 | 2231 | 290 | 275 | 28 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521041 | 468824 | 0 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12481 | 7 | 1715 | 1564 | 0 | 1578 | 10978 | 1428 | 0 | 2472 | 50 | 4610 | 12501 | 41 | 656 | 7 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 189 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
str d0, [x6], #0x10 str d0, [x7], #0x10 str d0, [x8], #0x10 str d0, [x9], #0x10 str d0, [x10], #0x10 str d0, [x11], #0x10 str d0, [x12], #0x10 str d0, [x13], #0x10
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5026
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 1e | 1f | 20 | 22 | 24 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80214 | 40220 | 301 | 5 | 5 | 5 | 0 | 9975 | 143 | 2298 | 2 | 0 | 1200 | 5 | 264 | 40155 | 2263 | 642 | 734 | 56 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1848860 | 0 | 2 | 40199 | 40239 | 40252 | 30140 | 3 | 30129 | 160100 | 200 | 80000 | 200 | 160000 | 40221 | 40211 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82464 | 45 | 2359 | 2405 | 20 | 2464 | 80057 | 1494 | 0 | 2466 | 956 | 4686 | 82486 | 56 | 2364 | 14 | 5 | 0 | 5110 | 2 | 16 | 2 | 2 | 40215 | 80002 | 80000 | 80100 | 40181 | 40163 | 40235 | 40169 | 40182 |
| 80204 | 40187 | 301 | 4 | 0 | 0 | 0 | 9861 | 76 | 2315 | 2 | 0 | 1224 | 12 | 264 | 40175 | 2278 | 935 | 773 | 67 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1847060 | 0 | 2 | 40184 | 40190 | 40173 | 30114 | 3 | 30174 | 160100 | 200 | 80000 | 200 | 160000 | 40220 | 40226 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82456 | 41 | 2803 | 2428 | 3 | 2444 | 80082 | 1492 | 5 | 2465 | 956 | 4638 | 82470 | 78 | 2669 | 14 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40194 | 80002 | 80000 | 80100 | 40217 | 40208 | 40154 | 40153 | 40229 |
| 80204 | 40212 | 301 | 5 | 5 | 5 | 0 | 9912 | 68 | 2290 | 2 | 0 | 1216 | 10 | 264 | 40194 | 2298 | 1045 | 756 | 67 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1848452 | 1 | 2 | 40173 | 40200 | 40239 | 30172 | 3 | 30151 | 160320 | 200 | 80000 | 200 | 160000 | 40180 | 40183 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82487 | 24 | 1901 | 2413 | 2 | 2467 | 80074 | 1542 | 3 | 2462 | 1212 | 4655 | 82492 | 53 | 2029 | 14 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40239 | 80002 | 80000 | 80100 | 40191 | 40233 | 40152 | 40184 | 40216 |
| 80204 | 40178 | 301 | 5 | 0 | 0 | 0 | 9882 | 81 | 2297 | 2 | 0 | 1224 | 15 | 264 | 40178 | 2277 | 913 | 888 | 102 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1844180 | 0 | 2 | 40155 | 40280 | 40204 | 30117 | 3 | 30164 | 160100 | 200 | 80000 | 200 | 160000 | 40171 | 40241 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82476 | 28 | 3038 | 2385 | 14 | 2454 | 80060 | 1525 | 0 | 2450 | 472 | 4597 | 82486 | 60 | 2376 | 14 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40185 | 80002 | 80000 | 80100 | 40183 | 40176 | 40199 | 40248 | 40190 |
| 80204 | 40192 | 301 | 4 | 0 | 0 | 0 | 9969 | 80 | 2305 | 2 | 0 | 1208 | 10 | 264 | 40167 | 2270 | 682 | 809 | 100 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1847636 | 1 | 2 | 40177 | 40211 | 40174 | 30084 | 3 | 30138 | 160100 | 200 | 80000 | 200 | 160000 | 40229 | 40182 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82471 | 36 | 2354 | 2395 | 8 | 2462 | 80067 | 1491 | 0 | 2465 | 958 | 4597 | 82504 | 75 | 2844 | 28 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40159 | 80002 | 80000 | 80100 | 40207 | 40185 | 40184 | 40253 | 40249 |
| 80204 | 40158 | 301 | 5 | 0 | 5 | 0 | 9720 | 88 | 2312 | 2 | 0 | 1240 | 12 | 264 | 40177 | 2264 | 822 | 795 | 74 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1847517 | 0 | 2 | 40137 | 40207 | 40197 | 30135 | 3 | 30224 | 160100 | 200 | 80000 | 200 | 160000 | 40183 | 40177 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82463 | 30 | 2623 | 2392 | 10 | 2446 | 80064 | 1512 | 0 | 2449 | 958 | 4535 | 82485 | 70 | 2571 | 14 | 4 | 0 | 5110 | 2 | 16 | 2 | 2 | 40200 | 80002 | 80000 | 80100 | 40199 | 40187 | 40228 | 40237 | 40211 |
| 80204 | 40229 | 301 | 5 | 0 | 0 | 0 | 9939 | 71 | 2312 | 2 | 0 | 1216 | 12 | 264 | 40184 | 2292 | 680 | 935 | 97 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1845596 | 0 | 2 | 40161 | 40229 | 40162 | 30094 | 3 | 30119 | 160100 | 200 | 80000 | 200 | 160000 | 40203 | 40215 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82476 | 28 | 2615 | 2395 | 19 | 2446 | 80068 | 1515 | 0 | 2442 | 956 | 4684 | 82480 | 59 | 2067 | 14 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40200 | 80002 | 80000 | 80100 | 40190 | 40202 | 40174 | 40217 | 40181 |
| 80204 | 40174 | 301 | 4 | 0 | 4 | 0 | 9816 | 111 | 2305 | 2 | 0 | 1224 | 13 | 264 | 40247 | 2381 | 977 | 930 | 80 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1848092 | 0 | 2 | 40184 | 40573 | 40187 | 30066 | 3 | 30133 | 160100 | 200 | 80000 | 200 | 160000 | 40217 | 40214 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82483 | 36 | 2081 | 2422 | 11 | 2433 | 80099 | 1507 | 0 | 2458 | 1634 | 4611 | 82484 | 72 | 2852 | 27 | 10 | 0 | 5110 | 2 | 16 | 2 | 2 | 40232 | 80002 | 80000 | 80100 | 40157 | 40204 | 40186 | 40228 | 40186 |
| 80204 | 40171 | 301 | 5 | 0 | 0 | 0 | 9951 | 100 | 2298 | 2 | 0 | 1232 | 9 | 264 | 40209 | 2291 | 754 | 656 | 91 | 25 | 160102 | 80102 | 80000 | 80234 | 80000 | 400531 | 1847636 | 1 | 2 | 40152 | 40171 | 40191 | 30088 | 3 | 30173 | 160100 | 200 | 80000 | 200 | 160000 | 40226 | 40178 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82464 | 32 | 2365 | 2401 | 6 | 2487 | 80062 | 1517 | 0 | 2465 | 956 | 4726 | 82494 | 59 | 2831 | 14 | 4 | 0 | 5110 | 2 | 16 | 2 | 2 | 40208 | 80002 | 80000 | 80100 | 40261 | 40156 | 40239 | 40187 | 40159 |
| 80204 | 40151 | 301 | 4 | 0 | 0 | 0 | 10020 | 79 | 2290 | 2 | 0 | 1200 | 9 | 264 | 40200 | 2376 | 775 | 824 | 100 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1845740 | 0 | 2 | 40176 | 40190 | 40185 | 30104 | 3 | 30177 | 160100 | 200 | 80000 | 200 | 160000 | 40184 | 40200 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82459 | 28 | 2144 | 2394 | 4 | 2457 | 80068 | 1510 | 0 | 2441 | 958 | 4627 | 82488 | 60 | 2372 | 14 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 40155 | 80002 | 80000 | 80100 | 40201 | 40220 | 40219 | 40175 | 40167 |
Result (median cycles for code divided by count): 0.5022
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 23 | 24 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80034 | 40209 | 371 | 1 | 1 | 0 | 0 | 0 | 0 | 10155 | 132 | 2307 | 1 | 0 | 0 | 1488 | 6 | 544 | 40136 | 2309 | 437 | 312 | 31 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1850828 | 0 | 0 | 2 | 40146 | 40173 | 40222 | 30088 | 3 | 30182 | 160010 | 20 | 80000 | 20 | 160000 | 40222 | 40162 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82504 | 14 | 1199 | 2498 | 3 | 2497 | 80036 | 1534 | 0 | 2486 | 754 | 4694 | 82556 | 70 | 1784 | 14 | 0 | 5020 | 0 | 15 | 17 | 0 | 9 | 12 | 40207 | 80002 | 0 | 80000 | 80010 | 40198 | 40144 | 40162 | 40216 | 40207 |
| 80024 | 40165 | 372 | 1 | 0 | 0 | 0 | 0 | 0 | 10269 | 83 | 2320 | 1 | 0 | 0 | 1496 | 7 | 420 | 40163 | 2232 | 825 | 738 | 43 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1847948 | 0 | 0 | 2 | 40145 | 40180 | 40102 | 30229 | 3 | 30214 | 160010 | 20 | 80000 | 20 | 160000 | 40873 | 40314 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82648 | 14 | 1768 | 2409 | 40 | 2473 | 80321 | 1467 | 0 | 2464 | 774 | 4632 | 82559 | 49 | 1765 | 0 | 0 | 5020 | 0 | 10 | 17 | 0 | 9 | 7 | 40131 | 80002 | 0 | 80000 | 80010 | 40308 | 40100 | 40185 | 40147 | 40186 |
| 80024 | 40174 | 348 | 0 | 0 | 0 | 0 | 0 | 0 | 9996 | 129 | 2252 | 1 | 0 | 0 | 1424 | 9 | 116 | 40151 | 2265 | 547 | 676 | 50 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843768 | 0 | 0 | 2 | 40298 | 40260 | 40268 | 30145 | 3 | 30096 | 160010 | 20 | 80000 | 20 | 160000 | 40139 | 40279 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82515 | 14 | 768 | 2447 | 2 | 2480 | 80102 | 1504 | 2 | 2488 | 816 | 4707 | 82542 | 84 | 1698 | 14 | 0 | 5020 | 0 | 7 | 17 | 0 | 11 | 10 | 40197 | 80002 | 0 | 80000 | 80010 | 40280 | 40140 | 40166 | 40123 | 40177 |
| 80024 | 40158 | 347 | 1 | 1 | 1 | 1 | 0 | 0 | 10059 | 142 | 2293 | 1 | 0 | 0 | 1256 | 9 | 260 | 40199 | 2288 | 755 | 348 | 32 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1843916 | 0 | 0 | 2 | 40177 | 40161 | 40190 | 30047 | 3 | 30149 | 160010 | 20 | 80000 | 20 | 160000 | 40161 | 40255 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82510 | 24 | 1116 | 2457 | 20 | 2463 | 80080 | 1523 | 0 | 2474 | 848 | 4662 | 82557 | 73 | 1454 | 14 | 0 | 5020 | 0 | 10 | 17 | 0 | 10 | 10 | 40098 | 80002 | 0 | 80000 | 80010 | 40128 | 40192 | 40302 | 40259 | 40143 |
| 80024 | 40115 | 348 | 1 | 1 | 0 | 0 | 0 | 0 | 9924 | 141 | 2268 | 0 | 0 | 1 | 992 | 8 | 452 | 40177 | 2279 | 591 | 624 | 47 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1849004 | 0 | 0 | 2 | 40166 | 40174 | 40122 | 30176 | 3 | 30137 | 160010 | 20 | 80000 | 20 | 160000 | 40206 | 40285 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82532 | 22 | 1389 | 2466 | 2 | 2474 | 80082 | 1546 | 0 | 2496 | 486 | 4732 | 82550 | 78 | 1670 | 14 | 0 | 5020 | 0 | 10 | 17 | 0 | 10 | 10 | 40166 | 80002 | 0 | 80000 | 80010 | 40192 | 40140 | 40176 | 40216 | 40184 |
| 80024 | 40185 | 323 | 1 | 0 | 2 | 2 | 0 | 0 | 10356 | 190 | 2346 | 0 | 0 | 1 | 1416 | 8 | 292 | 40209 | 2246 | 382 | 688 | 104 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1848664 | 0 | 0 | 2 | 40110 | 40155 | 40225 | 30088 | 3 | 30113 | 160010 | 20 | 80000 | 20 | 160000 | 40096 | 40114 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82496 | 0 | 1012 | 2398 | 1 | 2446 | 80055 | 1545 | 0 | 2510 | 996 | 4684 | 82544 | 83 | 1422 | 0 | 0 | 5020 | 0 | 11 | 17 | 0 | 11 | 11 | 40210 | 80002 | 0 | 80000 | 80010 | 40177 | 40201 | 40076 | 40133 | 40196 |
| 80024 | 40182 | 323 | 0 | 0 | 0 | 0 | 0 | 0 | 10329 | 156 | 2324 | 0 | 0 | 1 | 1248 | 5 | 500 | 40224 | 2262 | 880 | 574 | 36 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1846912 | 0 | 0 | 2 | 40146 | 40279 | 40153 | 30056 | 3 | 30163 | 160010 | 20 | 80000 | 20 | 160000 | 40105 | 40231 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82510 | 0 | 1495 | 2388 | 1 | 2508 | 80055 | 1496 | 0 | 2489 | 1010 | 4690 | 82565 | 48 | 1308 | 0 | 0 | 5020 | 0 | 10 | 17 | 0 | 11 | 10 | 40162 | 80002 | 0 | 80000 | 80010 | 40105 | 40123 | 40190 | 40144 | 40129 |
| 80024 | 40139 | 310 | 0 | 0 | 0 | 0 | 0 | 0 | 10257 | 101 | 2292 | 0 | 0 | 1 | 1472 | 2 | 516 | 40100 | 2272 | 706 | 385 | 63 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1847968 | 0 | 0 | 2 | 40186 | 40207 | 40177 | 30055 | 3 | 30172 | 160010 | 20 | 80000 | 20 | 160000 | 40207 | 40143 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82484 | 0 | 992 | 2457 | 7 | 2497 | 80093 | 1549 | 0 | 2488 | 1230 | 4710 | 82544 | 80 | 1554 | 0 | 0 | 5020 | 0 | 9 | 17 | 0 | 10 | 11 | 40103 | 80002 | 0 | 80000 | 80010 | 40196 | 40149 | 40238 | 40175 | 40237 |
| 80024 | 40132 | 311 | 0 | 0 | 0 | 0 | 0 | 0 | 10227 | 210 | 2316 | 0 | 0 | 1 | 1224 | 5 | 384 | 40151 | 2258 | 636 | 706 | 9 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843192 | 0 | 0 | 2 | 40209 | 40196 | 40112 | 30105 | 3 | 30121 | 160010 | 20 | 80000 | 20 | 160000 | 40104 | 40128 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82468 | 0 | 1420 | 2467 | 2 | 2442 | 80051 | 1532 | 0 | 2500 | 848 | 4648 | 82555 | 89 | 1125 | 0 | 1 | 5020 | 0 | 12 | 17 | 0 | 10 | 10 | 40177 | 80002 | 0 | 80000 | 80010 | 40175 | 40144 | 40142 | 40152 | 40138 |
| 80024 | 40198 | 306 | 0 | 0 | 0 | 0 | 0 | 0 | 10134 | 156 | 2348 | 0 | 0 | 1 | 1232 | 4 | 116 | 40200 | 2289 | 249 | 571 | 37 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1846600 | 0 | 0 | 2 | 40181 | 40239 | 40177 | 30084 | 3 | 30113 | 160010 | 20 | 80000 | 20 | 160000 | 40241 | 40210 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82502 | 0 | 1789 | 2480 | 1 | 2490 | 80079 | 1525 | 0 | 2488 | 756 | 4636 | 82556 | 63 | 968 | 0 | 0 | 5020 | 0 | 11 | 17 | 0 | 8 | 11 | 40197 | 80002 | 0 | 80000 | 80010 | 40182 | 40228 | 40211 | 40166 | 40109 |