Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
str q0, [x6], #0x10
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 8 | 0 | 0 | 0 | 0 | 12 | 8 | 42 | 1 | 3 | 0 | 1025 | 22 | 0 | 0 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1032 | 0 | 40 | 4 | 6 | 1003 | 1 | 0 | 4 | 26 | 4 | 1028 | 4 | 32 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 1 | 1 | 6 | 13 | 26 | 2 | 16 | 0 | 1025 | 8 | 0 | 6 | 10 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1039 | 32 | 48 | 0 | 0 | 1011 | 4 | 1 | 0 | 0 | 10 | 1004 | 11 | 36 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 1 | 0 | 15 | 34 | 1 | 2 | 12 | 1025 | 0 | 0 | 5 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1019 | 15 | 48 | 0 | 1 | 1011 | 1 | 1 | 42 | 16 | 17 | 1043 | 12 | 44 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 1 | 30 | 15 | 36 | 1 | 5 | 0 | 1025 | 14 | 7 | 0 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1042 | 9 | 61 | 4 | 11 | 1012 | 1 | 2 | 0 | 0 | 14 | 1030 | 12 | 40 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 0 | 1 | 0 | 15 | 32 | 1 | 16 | 0 | 1025 | 12 | 0 | 3 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1017 | 20 | 36 | 0 | 0 | 1011 | 0 | 0 | 0 | 0 | 11 | 1004 | 11 | 40 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 1 | 0 | 0 | 0 | 15 | 26 | 2 | 19 | 0 | 1025 | 24 | 6 | 4 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1008 | 8 | 48 | 5 | 35 | 1014 | 1 | 1 | 50 | 32 | 14 | 1048 | 11 | 36 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 1 | 0 | 0 | 0 | 15 | 0 | 0 | 18 | 0 | 1025 | 34 | 1 | 2 | 8 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1050 | 7 | 44 | 4 | 36 | 1011 | 0 | 1 | 40 | 16 | 11 | 1031 | 11 | 44 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 20 | 0 | 1025 | 20 | 3 | 3 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50770 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1042 | 0 | 41 | 4 | 12 | 1001 | 0 | 0 | 40 | 32 | 7 | 1044 | 4 | 36 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 1 | 0 | 1 | 6 | 7 | 32 | 1 | 2 | 0 | 1025 | 34 | 6 | 2 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1034 | 0 | 44 | 1 | 24 | 1004 | 2 | 0 | 32 | 24 | 7 | 1047 | 4 | 16 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 0 | 0 | 0 | 8 | 38 | 1 | 21 | 0 | 1025 | 34 | 4 | 5 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1040 | 0 | 52 | 0 | 6 | 1004 | 0 | 0 | 0 | 0 | 0 | 1004 | 4 | 28 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
str q0, [x6], #0x10
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | c3 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10214 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10485 | 62 | 2306 | 1 | 1728 | 2 | 0 | 1188 | 10025 | 2265 | 0 | 192 | 226 | 23 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522195 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12477 | 0 | 1647 | 1450 | 0 | 1441 | 11044 | 1509 | 0 | 2476 | 50 | 4508 | 12509 | 26 | 630 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 163 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10311 | 59 | 2263 | 1 | 1480 | 0 | 0 | 968 | 10025 | 2224 | 1 | 239 | 202 | 25 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12490 | 4 | 1607 | 1494 | 0 | 1542 | 11011 | 1524 | 0 | 2489 | 50 | 4532 | 12509 | 28 | 735 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 333 | 0 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10548 | 47 | 2262 | 1 | 1400 | 1 | 0 | 712 | 10025 | 2217 | 0 | 225 | 193 | 21 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522147 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12485 | 0 | 1602 | 1497 | 0 | 1488 | 11033 | 1503 | 0 | 2461 | 50 | 4555 | 12508 | 17 | 616 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 208 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10521 | 50 | 2263 | 1 | 1432 | 2 | 2 | 776 | 10025 | 2224 | 0 | 184 | 186 | 27 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522179 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12465 | 0 | 1772 | 1522 | 0 | 1444 | 10990 | 1524 | 0 | 2493 | 50 | 4541 | 12496 | 27 | 625 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 202 | 0 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 0 | 1 | 0 | 0 | 10380 | 45 | 2263 | 1 | 1440 | 2 | 1 | 752 | 10025 | 2239 | 0 | 230 | 218 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522165 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12477 | 0 | 1633 | 1545 | 0 | 1522 | 11010 | 1494 | 0 | 2485 | 50 | 4597 | 12515 | 19 | 662 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 283 | 0 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 1 | 0 | 0 | 0 | 0 | 0 | 10521 | 60 | 2282 | 1 | 1672 | 1 | 1 | 1028 | 10025 | 2273 | 0 | 185 | 189 | 15 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522149 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12469 | 0 | 1737 | 1467 | 0 | 1528 | 10957 | 1512 | 0 | 2473 | 50 | 4584 | 12509 | 25 | 691 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 145 | 5 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10329 | 61 | 2263 | 1 | 1720 | 5 | 1 | 960 | 10025 | 2247 | 0 | 200 | 232 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522187 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12473 | 0 | 1612 | 1505 | 0 | 1456 | 10987 | 1513 | 0 | 2493 | 50 | 4553 | 12516 | 28 | 629 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 146 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10077 | 75 | 1 | 1 | 0 | 0 | 0 | 0 | 10434 | 69 | 2301 | 1 | 1704 | 8 | 1 | 724 | 10025 | 2229 | 0 | 205 | 217 | 20 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522155 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12497 | 0 | 1545 | 1492 | 0 | 1534 | 10990 | 1520 | 0 | 2493 | 50 | 4563 | 12485 | 21 | 665 | 1 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 319 | 3 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10476 | 56 | 2271 | 1 | 1592 | 1 | 1 | 1020 | 10025 | 2270 | 0 | 213 | 205 | 20 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522171 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12481 | 4 | 1578 | 1508 | 0 | 1536 | 11002 | 1504 | 0 | 2461 | 50 | 4662 | 12505 | 25 | 654 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 298 | 7 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 10392 | 64 | 2279 | 1 | 1704 | 5 | 0 | 964 | 10025 | 2232 | 0 | 195 | 243 | 20 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522195 | 468824 | 10016 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12481 | 0 | 1703 | 1414 | 0 | 1477 | 11053 | 1491 | 0 | 2477 | 50 | 4548 | 12499 | 26 | 709 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 240 | 6 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 1e | 1f | 20 | 22 | 23 | 24 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10034 | 10040 | 75 | 2 | 2 | 0 | 2 | 0 | 9960 | 58 | 2297 | 1 | 0 | 0 | 1968 | 3 | 0 | 956 | 10025 | 2261 | 4 | 217 | 268 | 25 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521041 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12457 | 8 | 1716 | 1556 | 0 | 1554 | 10949 | 1524 | 0 | 2481 | 50 | 4604 | 12502 | 32 | 933 | 4 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 389 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 2 | 2 | 0 | 10176 | 75 | 2291 | 1 | 0 | 0 | 1432 | 5 | 0 | 756 | 10025 | 2230 | 0 | 254 | 227 | 33 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521033 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12473 | 16 | 1651 | 1504 | 0 | 1533 | 10956 | 1518 | 0 | 2477 | 50 | 4657 | 12501 | 30 | 746 | 4 | 640 | 3 | 16 | 3 | 4 | 10078 | 10000 | 355 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 0 | 10347 | 71 | 2294 | 1 | 0 | 0 | 1496 | 4 | 0 | 776 | 10025 | 2244 | 0 | 198 | 216 | 32 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520745 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12477 | 9 | 1970 | 1502 | 0 | 1574 | 10943 | 1513 | 0 | 2485 | 50 | 4507 | 12500 | 32 | 774 | 0 | 640 | 4 | 16 | 4 | 3 | 10037 | 10000 | 298 | 4 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 1 | 0 | 10161 | 73 | 2312 | 1 | 0 | 0 | 1416 | 6 | 0 | 952 | 10025 | 2271 | 0 | 221 | 238 | 28 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12481 | 9 | 1589 | 1532 | 0 | 1577 | 10943 | 1513 | 1 | 2493 | 50 | 4557 | 12507 | 34 | 767 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 352 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 1 | 0 | 0 | 1 | 0 | 10173 | 69 | 2260 | 1 | 0 | 0 | 1440 | 2 | 0 | 924 | 10127 | 2242 | 0 | 259 | 249 | 40 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521105 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12471 | 8 | 1622 | 1566 | 0 | 1548 | 10941 | 1521 | 0 | 2484 | 50 | 4655 | 12491 | 29 | 849 | 0 | 640 | 3 | 16 | 4 | 4 | 10037 | 10000 | 190 | 6 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 1 | 1 | 0 | 10245 | 72 | 2297 | 1 | 0 | 0 | 1680 | 5 | 0 | 880 | 10025 | 2274 | 1 | 210 | 209 | 34 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520953 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12491 | 8 | 1646 | 1548 | 0 | 1572 | 10960 | 1515 | 0 | 2484 | 50 | 4610 | 12518 | 34 | 705 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 193 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 0 | 10104 | 65 | 2291 | 1 | 0 | 0 | 1512 | 9 | 0 | 912 | 10025 | 2238 | 0 | 226 | 232 | 36 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521081 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12493 | 23 | 1671 | 1530 | 0 | 1577 | 10964 | 1514 | 0 | 2477 | 50 | 4528 | 12484 | 26 | 830 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 191 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 3 | 0 | 3 | 0 | 0 | 10140 | 57 | 2302 | 1 | 0 | 0 | 1512 | 8 | 0 | 912 | 10025 | 2249 | 0 | 220 | 238 | 32 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521049 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12500 | 24 | 1802 | 1532 | 0 | 1572 | 10953 | 1495 | 6 | 2477 | 50 | 4621 | 12501 | 33 | 603 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 405 | 8 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 2 | 0 | 0 | 10362 | 73 | 2291 | 1 | 0 | 0 | 1496 | 7 | 0 | 964 | 10025 | 2266 | 0 | 266 | 230 | 25 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12495 | 18 | 1659 | 1551 | 0 | 1587 | 10940 | 1506 | 0 | 2500 | 50 | 4524 | 12492 | 27 | 773 | 0 | 640 | 4 | 16 | 3 | 3 | 10037 | 10000 | 269 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 2 | 2 | 2 | 0 | 10026 | 58 | 2285 | 1 | 0 | 0 | 1480 | 5 | 0 | 936 | 10025 | 2263 | 0 | 237 | 173 | 38 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 10021 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12487 | 18 | 1644 | 1521 | 0 | 1585 | 10931 | 1536 | 2 | 2484 | 50 | 4636 | 12505 | 33 | 691 | 0 | 640 | 4 | 16 | 3 | 3 | 10037 | 10000 | 319 | 4 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
str q0, [x6], #0x10 str q0, [x7], #0x10 str q0, [x8], #0x10 str q0, [x9], #0x10 str q0, [x10], #0x10 str q0, [x11], #0x10 str q0, [x12], #0x10 str q0, [x13], #0x10
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5021
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 24 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 61 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | c3 | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80214 | 40102 | 301 | 1 | 0 | 0 | 0 | 0 | 10191 | 118 | 2293 | 1 | 0 | 1704 | 12 | 200 | 40109 | 2293 | 734 | 557 | 50 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1846936 | 0 | 0 | 2 | 40177 | 40206 | 40170 | 30079 | 3 | 30126 | 160100 | 200 | 80000 | 200 | 160000 | 40237 | 40166 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82493 | 8 | 1101 | 2452 | 11 | 2471 | 80041 | 1550 | 0 | 2476 | 762 | 4691 | 82541 | 74 | 1247 | 0 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40149 | 80002 | 80000 | 80100 | 40161 | 40199 | 40118 | 40137 | 40101 |
| 80204 | 40180 | 302 | 1 | 0 | 0 | 0 | 0 | 9885 | 157 | 2300 | 1 | 0 | 1256 | 9 | 208 | 40202 | 2306 | 737 | 553 | 50 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844968 | 0 | 0 | 2 | 40158 | 40175 | 40197 | 30123 | 3 | 30083 | 160100 | 200 | 80000 | 200 | 160000 | 40236 | 40171 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82507 | 16 | 1851 | 2455 | 18 | 2478 | 80089 | 1518 | 0 | 2453 | 316 | 4671 | 82540 | 72 | 1488 | 2 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40143 | 80002 | 80000 | 80100 | 40213 | 40251 | 40186 | 40204 | 40151 |
| 80204 | 40153 | 300 | 1 | 0 | 0 | 0 | 0 | 10008 | 176 | 2219 | 1 | 0 | 1264 | 12 | 124 | 40146 | 2310 | 643 | 674 | 30 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1842568 | 0 | 0 | 2 | 40132 | 40187 | 40198 | 29994 | 3 | 30240 | 160320 | 200 | 80000 | 200 | 160000 | 40241 | 40190 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82501 | 8 | 1457 | 2454 | 3 | 2494 | 80092 | 1508 | 0 | 2496 | 986 | 4678 | 82546 | 114 | 1068 | 0 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40214 | 80002 | 80000 | 80100 | 40168 | 40185 | 40188 | 40173 | 40184 |
| 80204 | 40152 | 300 | 2 | 0 | 0 | 0 | 0 | 10194 | 72 | 2288 | 1 | 0 | 1288 | 9 | 144 | 40178 | 2314 | 471 | 646 | 40 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1845976 | 0 | 0 | 2 | 40188 | 40160 | 40192 | 30082 | 3 | 30135 | 160100 | 200 | 80000 | 200 | 160000 | 40225 | 40195 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82502 | 16 | 1944 | 2472 | 5 | 2498 | 80043 | 1543 | 2 | 2479 | 884 | 4826 | 82541 | 65 | 1438 | 2 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40116 | 80002 | 80000 | 80100 | 40166 | 40187 | 40215 | 40214 | 40156 |
| 80204 | 40189 | 302 | 1 | 0 | 0 | 0 | 0 | 10239 | 133 | 2284 | 1 | 0 | 1216 | 13 | 104 | 40118 | 2291 | 539 | 789 | 49 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1842040 | 0 | 0 | 2 | 40197 | 40172 | 40218 | 30176 | 3 | 30154 | 160100 | 200 | 80000 | 200 | 160000 | 40122 | 40220 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82483 | 8 | 1884 | 2413 | 5 | 2495 | 80092 | 1501 | 0 | 2492 | 1002 | 4655 | 82541 | 96 | 1221 | 1 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40161 | 80002 | 80000 | 80100 | 40231 | 40159 | 40108 | 40183 | 40168 |
| 80204 | 40189 | 300 | 1 | 0 | 0 | 0 | 0 | 10323 | 78 | 2291 | 1 | 0 | 1384 | 8 | 204 | 40160 | 2264 | 531 | 568 | 59 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1845064 | 0 | 0 | 2 | 40112 | 40162 | 40166 | 30020 | 3 | 30149 | 160325 | 200 | 80000 | 200 | 160000 | 40245 | 41377 | 11 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82900 | 16 | 3044 | 2399 | 287 | 2435 | 80670 | 1555 | 0 | 2500 | 806 | 12041 | 83076 | 72 | 1212 | 0 | 0 | 5289 | 0 | 3 | 96 | 3 | 2 | 41363 | 81129 | 80000 | 80100 | 41238 | 41490 | 41309 | 41352 | 41071 |
| 80204 | 41612 | 312 | 1 | 0 | 1 | 11 | 10 | 11082 | 1001 | 2272 | 1 | 0 | 1408 | 14 | 780 | 41511 | 2202 | 805 | 817 | 862 | 260 | 161830 | 80558 | 80600 | 80892 | 81080 | 406778 | 1891612 | 0 | 0 | 2 | 41341 | 41549 | 41277 | 31019 | 44 | 30874 | 162316 | 200 | 81212 | 200 | 162184 | 41533 | 41585 | 11 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 83114 | 10 | 1803 | 2437 | 295 | 2458 | 80733 | 1542 | 0 | 2484 | 476 | 12305 | 83162 | 115 | 1611 | 0 | 0 | 5353 | 0 | 3 | 121 | 3 | 4 | 41227 | 81584 | 80000 | 80100 | 41953 | 41741 | 41905 | 41908 | 42057 |
| 80204 | 40235 | 301 | 1 | 1 | 1 | 0 | 0 | 10149 | 59 | 2309 | 1 | 0 | 1296 | 9 | 600 | 40206 | 2236 | 458 | 689 | 41 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844968 | 1 | 0 | 2 | 40200 | 40232 | 40231 | 30095 | 3 | 30161 | 160100 | 200 | 80000 | 200 | 160000 | 40187 | 40165 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82488 | 9 | 1931 | 2457 | 3 | 2500 | 80094 | 1493 | 0 | 2498 | 986 | 4730 | 82516 | 107 | 1090 | 0 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40166 | 80002 | 80000 | 80100 | 40143 | 40129 | 40191 | 40292 | 40126 |
| 80204 | 40223 | 301 | 1 | 1 | 0 | 0 | 0 | 10347 | 117 | 2308 | 1 | 0 | 1264 | 11 | 208 | 40163 | 2306 | 757 | 730 | 21 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1848040 | 0 | 0 | 2 | 40140 | 40226 | 40194 | 30107 | 3 | 30179 | 160100 | 200 | 80000 | 200 | 160000 | 40254 | 40214 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82479 | 9 | 1893 | 2461 | 5 | 2464 | 80107 | 1537 | 0 | 2488 | 976 | 4730 | 82539 | 55 | 1020 | 0 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40263 | 80002 | 80000 | 80100 | 40241 | 40266 | 40193 | 40143 | 40188 |
| 80204 | 40207 | 301 | 2 | 2 | 2 | 0 | 0 | 10206 | 70 | 2342 | 1 | 0 | 1264 | 17 | 436 | 40118 | 2283 | 634 | 356 | 66 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1847032 | 0 | 0 | 2 | 40165 | 40113 | 40165 | 30158 | 3 | 30166 | 160100 | 200 | 80000 | 200 | 160000 | 40204 | 40204 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82499 | 9 | 1439 | 2469 | 5 | 2469 | 80070 | 1510 | 1 | 2476 | 740 | 4740 | 82539 | 83 | 2015 | 1 | 0 | 5110 | 0 | 2 | 16 | 2 | 2 | 40136 | 80002 | 80000 | 80100 | 40172 | 40193 | 40263 | 40204 | 40116 |
Result (median cycles for code divided by count): 0.5019
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 24 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d5 | map dispatch bubble (d6) | d9 | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80034 | 40163 | 301 | 2 | 0 | 0 | 2 | 9543 | 43 | 2280 | 1 | 0 | 1488 | 5 | 284 | 40246 | 2225 | 373 | 477 | 55 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843456 | 0 | 2 | 40094 | 40147 | 40133 | 30114 | 3 | 30091 | 160010 | 20 | 80000 | 20 | 160000 | 40135 | 40121 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82476 | 12 | 1888 | 2421 | 2 | 2488 | 80031 | 1504 | 0 | 2484 | 740 | 4592 | 82510 | 30 | 1950 | 0 | 2 | 5020 | 0 | 7 | 17 | 0 | 0 | 6 | 7 | 40158 | 80002 | 80000 | 80010 | 40123 | 40125 | 40125 | 40114 | 40125 |
| 80024 | 40141 | 301 | 2 | 0 | 0 | 0 | 9993 | 45 | 2291 | 1 | 0 | 1440 | 5 | 216 | 40127 | 2316 | 809 | 597 | 211 | 87 | 160356 | 80348 | 80180 | 80234 | 80324 | 401767 | 1853464 | 0 | 2 | 40389 | 40514 | 40671 | 30392 | 23 | 30372 | 160670 | 20 | 80240 | 20 | 160720 | 40675 | 40966 | 3 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82674 | 14 | 1736 | 2426 | 93 | 2470 | 80226 | 1499 | 0 | 2472 | 764 | 6849 | 82746 | 33 | 1806 | 0 | 0 | 5056 | 0 | 5 | 33 | 0 | 0 | 5 | 5 | 40213 | 80002 | 80000 | 80010 | 40149 | 40133 | 40125 | 40149 | 40209 |
| 80024 | 40158 | 300 | 2 | 2 | 2 | 0 | 9978 | 52 | 2333 | 1 | 0 | 1424 | 8 | 108 | 40119 | 2261 | 604 | 586 | 65 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1847032 | 0 | 2 | 40149 | 40141 | 40197 | 30091 | 3 | 30110 | 160010 | 20 | 80000 | 20 | 160000 | 40142 | 40115 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82496 | 8 | 1580 | 2477 | 5 | 2476 | 80038 | 1523 | 1 | 2508 | 756 | 4442 | 82514 | 41 | 1394 | 0 | 0 | 5020 | 0 | 3 | 17 | 0 | 0 | 5 | 6 | 40122 | 80002 | 80000 | 80010 | 40158 | 40146 | 40137 | 40137 | 40129 |
| 80024 | 40133 | 301 | 1 | 0 | 0 | 0 | 10044 | 30 | 2345 | 1 | 0 | 1472 | 5 | 256 | 40164 | 2252 | 763 | 685 | 88 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843432 | 0 | 2 | 40107 | 40170 | 40178 | 30089 | 3 | 30080 | 160010 | 20 | 80000 | 20 | 160000 | 40146 | 40140 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82485 | 8 | 1707 | 2443 | 4 | 2483 | 80029 | 1542 | 1 | 2462 | 1034 | 4630 | 82506 | 34 | 1997 | 0 | 0 | 5020 | 0 | 5 | 16 | 0 | 0 | 5 | 3 | 40114 | 80002 | 80000 | 80010 | 40150 | 40191 | 40174 | 40106 | 40143 |
| 80024 | 40175 | 301 | 1 | 0 | 1 | 0 | 9729 | 36 | 2348 | 1 | 0 | 1448 | 6 | 176 | 40092 | 2271 | 535 | 780 | 54 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1845424 | 0 | 2 | 40105 | 40152 | 40124 | 30105 | 3 | 30109 | 160010 | 20 | 80000 | 20 | 160000 | 40158 | 40126 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82486 | 9 | 1771 | 2431 | 4 | 2484 | 80036 | 1539 | 0 | 2480 | 750 | 4597 | 82497 | 43 | 1603 | 0 | 0 | 5020 | 0 | 5 | 17 | 0 | 0 | 6 | 5 | 40136 | 80002 | 80000 | 80010 | 40171 | 40167 | 40149 | 40175 | 40138 |
| 80024 | 40102 | 300 | 1 | 1 | 1 | 1 | 9747 | 57 | 2317 | 1 | 0 | 1240 | 8 | 436 | 40139 | 2268 | 706 | 634 | 47 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1846048 | 0 | 2 | 40069 | 40189 | 40148 | 30092 | 3 | 30150 | 160010 | 20 | 80000 | 20 | 160000 | 40171 | 40170 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82468 | 8 | 2549 | 2451 | 4 | 2487 | 80044 | 1557 | 1 | 2488 | 976 | 4614 | 82501 | 42 | 1934 | 0 | 0 | 5020 | 0 | 5 | 16 | 0 | 0 | 3 | 5 | 40178 | 80002 | 80000 | 80010 | 40143 | 40165 | 40132 | 40166 | 40156 |
| 80024 | 40177 | 301 | 1 | 1 | 1 | 0 | 10179 | 49 | 2296 | 1 | 0 | 1272 | 10 | 296 | 40108 | 2303 | 725 | 557 | 37 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1844464 | 0 | 2 | 40121 | 40177 | 40103 | 30099 | 3 | 30112 | 160010 | 20 | 80000 | 20 | 160000 | 40171 | 40151 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82483 | 10 | 2121 | 2430 | 1 | 2478 | 80048 | 1519 | 0 | 2492 | 756 | 4544 | 82504 | 41 | 1889 | 0 | 0 | 5020 | 0 | 6 | 17 | 0 | 0 | 3 | 5 | 40175 | 80002 | 80000 | 80010 | 40135 | 40140 | 40213 | 40177 | 40144 |
| 80024 | 40175 | 300 | 1 | 0 | 0 | 0 | 9984 | 52 | 2300 | 1 | 0 | 1416 | 11 | 304 | 40130 | 2281 | 541 | 495 | 67 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843672 | 0 | 2 | 40144 | 40134 | 40146 | 30077 | 3 | 30112 | 160010 | 20 | 80000 | 20 | 160000 | 40130 | 40133 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82474 | 8 | 1727 | 2461 | 10 | 2456 | 80040 | 1545 | 2 | 2476 | 884 | 4669 | 82511 | 25 | 1749 | 0 | 1 | 5020 | 0 | 6 | 17 | 0 | 0 | 3 | 5 | 40146 | 80002 | 80000 | 80010 | 40128 | 40108 | 40142 | 40184 | 40134 |
| 80024 | 40177 | 301 | 1 | 0 | 1 | 1 | 9873 | 39 | 2300 | 1 | 0 | 1248 | 12 | 324 | 40157 | 2343 | 506 | 559 | 31 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843744 | 0 | 2 | 40073 | 40130 | 40194 | 30112 | 3 | 30115 | 160010 | 20 | 80000 | 20 | 160000 | 40118 | 40197 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82486 | 10 | 1394 | 2460 | 15 | 2487 | 80037 | 1540 | 0 | 2484 | 748 | 4581 | 82515 | 43 | 1658 | 0 | 1 | 5020 | 0 | 5 | 17 | 0 | 0 | 4 | 5 | 40117 | 80002 | 80000 | 80010 | 40188 | 40166 | 40193 | 40179 | 40257 |
| 80024 | 40160 | 300 | 1 | 0 | 1 | 1 | 9861 | 56 | 2322 | 1 | 0 | 1400 | 9 | 156 | 40131 | 2294 | 432 | 383 | 35 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843000 | 0 | 2 | 40084 | 40126 | 40294 | 30099 | 3 | 30112 | 160010 | 20 | 80000 | 20 | 160000 | 40159 | 40105 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82506 | 9 | 1502 | 2468 | 2 | 2473 | 80042 | 1513 | 1 | 2488 | 1084 | 4512 | 82506 | 31 | 980 | 0 | 0 | 5020 | 0 | 3 | 16 | 0 | 0 | 5 | 5 | 40082 | 80002 | 80000 | 80010 | 40122 | 40118 | 40138 | 40109 | 40142 |