Firestorm: STR (post-index, S) measurements

Code:

  str s0, [x6], #0x10

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	20	22	23	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	0	0	0	12	6	12	1	0	0	15	0	1025	36	1	1	2	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1036	0	52	8	9	1007	0	0	16	5	1038	4	40	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	0	9	12	0	0	0	2	0	1025	34	0	0	3	25	2000	1000	1000	1000	1000	50770	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1024	0	44	5	32	1005	1	24	32	7	1060	0	44	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	6	9	24	1	0	24	15	0	1025	14	1	0	4	25	2000	1000	1000	1000	1000	50770	45824	0	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1036	0	48	7	9	1009	0	28	20	10	1044	4	40	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	12	5	4	0	0	0	0	0	1025	0	0	1	6	25	2000	1000	1000	1000	1000	50770	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1016	0	20	3	6	1007	1	32	24	4	1036	4	28	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1092
1004	1040	7	0	0	1	0	6	38	1	0	0	19	0	1025	22	1	1	3	25	2000	1000	1000	1000	1000	50778	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1028	0	40	4	6	1008	0	0	0	9	1028	4	32	73	2	16	2	2	1037	1000	1	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	1	0	0	7	32	1	0	0	18	0	1025	28	0	0	5	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1024	0	36	4	22	1026	0	38	32	4	1052	0	56	73	2	16	2	2	1037	1000	1	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	12	6	38	1	0	0	23	0	1025	20	3	1	4	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1038	0	52	4	24	1004	1	38	30	4	1036	4	24	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	0	8	24	1	0	0	23	4	1025	0	0	1	4	25	2000	1000	1000	1000	1000	50770	45824	0	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1026	0	36	2	24	1004	1	30	40	7	1038	4	24	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	12	5	16	1	0	0	14	4	1025	16	0	0	2	25	2000	1000	1000	1000	1000	50770	45824	0	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1000	0	36	0	24	1006	3	24	8	3	1004	4	28	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	12	9	40	1	0	0	22	0	1025	18	0	1	3	25	2000	1000	1000	1000	1000	50762	45824	1	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1048	0	24	3	26	1003	0	12	0	10	1036	4	40	73	2	16	2	2	1037	1000	0	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 3->3

Code:

  str s0, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10214	10040	75	0	0	1	0	0	0	10404	46	2268	1	1720	1	4	724	10025	2229	219	233	26	25	20100	10100	10000	10100	10000	522187	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12469	4	1688	1547	0	1505	10983	1483	0	2489	50	4678	12498	26	657	0	0	0	0	710	1	17	1	1	10037	10000	336	7	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	1	0	0	10383	41	2261	1	1704	6	2	724	10025	2229	205	210	28	25	20100	10100	10000	10100	10000	522187	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12489	5	1587	1489	0	1527	11003	1510	1	2489	102	4582	12503	32	807	0	1	0	0	710	1	17	1	1	10037	10000	297	12	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	1	0	0	10422	50	2270	1	1688	6	0	724	10025	2229	213	207	30	25	20100	10100	10000	10100	10000	522203	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12483	4	1522	1459	9	1521	11013	1517	0	2489	50	4530	12516	25	666	0	0	0	0	710	1	17	1	1	10037	10000	380	4	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	76	1	0	0	0	0	0	10377	71	2282	1	1712	4	1	724	10025	2229	256	198	32	25	20100	10100	10000	10100	10000	522173	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12481	5	1625	1481	0	1516	11012	1505	1	2489	50	4584	12494	33	699	0	2	0	0	710	1	17	1	1	10037	10000	253	5	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	1	0	0	10416	50	2268	1	1680	5	0	724	10025	2238	221	219	25	25	20100	10100	10000	10100	10000	522171	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12473	5	1646	1488	0	1529	10997	1529	1	2465	50	4515	12510	25	700	0	1	0	0	710	1	17	1	1	10037	10000	202	5	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	1	0	0	10359	45	2268	1	1712	6	0	724	10025	2222	229	214	26	25	20100	10100	10000	10100	10000	522179	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12474	4	1609	1475	0	1539	10985	1477	0	2489	50	4476	12495	28	652	0	0	0	0	710	1	17	1	1	10037	10000	279	3	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	0	0	0	10554	62	2268	1	1712	6	1	724	10025	2236	194	220	16	25	20100	10100	10000	10100	10000	522155	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12484	4	1687	1510	0	1522	10968	1503	1	2480	50	4604	12498	29	794	0	0	0	0	710	1	17	1	1	10037	10000	222	3	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	0	0	0	10485	78	2263	1	1696	5	1	712	10025	2222	222	210	22	25	20100	10100	10000	10100	10000	522163	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12490	4	1697	1510	0	1513	10989	1542	2	2489	50	4615	12489	32	629	0	0	0	0	710	1	17	1	1	10037	10000	239	4	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	0	0	0	10479	52	2282	1	1704	2	0	712	10025	2229	206	366	20	25	20100	10100	10000	10100	10000	522187	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12473	15	1664	1504	0	1525	10981	1512	2	2489	50	4545	12507	29	695	0	0	0	0	710	1	17	1	1	10037	10000	345	1	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	1	0	0	10545	46	2269	1	1696	4	0	712	10025	2229	179	212	22	25	20100	10100	10000	10100	10000	522179	468824	10016	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12490	7	1627	1468	0	1524	10997	1525	2	2489	50	4528	12521	27	615	0	3	0	0	710	1	17	1	1	10037	10000	232	4	1	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3b	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10034	10040	75	1	0	1	10299	44	2339	1	1704	4	0	0	712	10025	2269	222	198	30	25	20010	10010	10000	10010	10000	521097	468824	1	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12501	8	1635	1478	0	1527	11068	1548	0	2496	50	4576	12516	20	659	0	0	640	0	0	3	16	3	3	10037	10000	250	3	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	0	0	0	10323	43	2309	1	1472	8	0	0	748	10025	2244	195	204	23	25	20010	10010	10000	10010	10000	521129	468824	1	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12499	11	1729	1503	0	1482	11040	1516	0	2481	50	4614	12504	25	608	7	0	640	0	0	3	16	3	3	10037	10000	246	7	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	2	10149	57	2374	1	1440	9	0	0	760	10025	2260	183	222	44	25	20010	10010	10000	10010	10000	521121	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12506	15	1667	1470	0	1501	10967	1497	1	2488	50	4578	12503	23	690	7	4	640	0	0	2	16	3	2	10037	10000	156	2	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	1	10623	52	2321	1	1664	11	0	0	1004	10025	2242	203	189	21	25	20010	10010	10000	10010	10000	521105	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12508	15	1636	1531	0	1476	11046	1529	0	2500	50	4622	12515	35	584	7	0	640	0	0	3	16	2	3	10037	10000	179	5	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	76	2	0	0	10116	48	2330	1	1472	8	0	0	760	10025	2273	190	235	20	25	20010	10010	10000	10010	10000	521097	468824	1	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12496	15	1545	1482	0	1492	11040	1518	2	2480	50	4531	12520	41	703	7	0	640	0	0	3	16	3	3	10037	10000	166	2	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	10407	47	2345	1	1696	3	0	2	956	10025	2235	188	193	43	25	20010	10010	10000	10010	10000	521121	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12515	8	1670	1492	0	1458	11046	1504	2	2493	50	4635	12506	30	674	7	0	640	0	0	3	16	2	3	10037	10000	274	3	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	10410	51	2315	1	1640	4	0	0	804	10025	2243	194	156	17	25	20010	10010	10000	10010	10000	521073	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12492	14	1680	1506	0	1482	11054	1517	0	2488	50	4461	12510	33	731	7	0	640	0	0	2	16	3	3	10037	10000	245	3	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	10404	37	2299	1	1632	2	0	0	1204	10025	2243	194	212	34	25	20010	10010	10000	10010	10000	521105	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12487	15	1625	1487	0	1532	11049	1503	2	2480	50	4657	12514	29	647	7	2	640	0	0	3	16	3	3	10037	10000	155	5	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	2	2	10458	65	2309	1	1464	6	0	0	1236	10025	2271	210	253	17	25	20010	10010	10000	10010	10000	521097	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12493	9	1665	1531	0	1548	11020	1534	0	2493	50	4642	12516	28	595	0	0	640	0	0	3	16	3	3	10037	10000	209	9	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	10263	44	2327	1	1480	1	0	1	764	10025	2284	222	231	27	25	20010	10010	10000	10010	10000	521129	468824	0	0	10016	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12501	8	1664	1473	0	1473	11019	1511	0	2476	50	4547	12496	28	571	0	0	640	0	0	2	33	2	3	10037	10000	289	3	1	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  str s0, [x6], #0x10
  str s0, [x7], #0x10
  str s0, [x8], #0x10
  str s0, [x9], #0x10
  str s0, [x10], #0x10
  str s0, [x11], #0x10
  str s0, [x12], #0x10
  str s0, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5028

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80214	40140	300	7	0	2	0	0	9963	53	2361	1	0	0	1264	13	268	40116	2302	713	514	50	25	160102	80102	80000	80100	80000	400535	1844344	0	2	40099	40191	40110	30005	3	30059	160100	200	80000	200	160000	40097	40110	1	1	80201	100	99	100	100	80000	80000	100	82471	9	1327	2456	0	2488	80050	1514	0	2494	822	4658	82507	23	1762	0	0	0	5110	1	16	1	1	40120	80002	80000	80100	40122	40156	40122	40137	40140
80204	40120	300	4	2	2	0	0	9942	49	2320	1	0	0	1456	11	480	40122	2259	622	527	40	25	160102	80102	80000	80100	80000	400535	1844584	1	2	40113	40113	40170	30036	3	30085	160100	200	80000	200	160000	40180	40127	1	1	80201	100	99	100	100	80000	80000	100	82477	16	1831	2471	4	2507	80042	1549	6	2482	898	4562	82507	20	1591	0	0	0	5110	1	16	1	1	40130	80002	80000	80100	40143	40181	40134	40211	40124
80204	40143	301	4	2	0	0	0	10143	67	2317	1	0	0	1480	9	268	40102	2279	731	638	34	25	160102	80102	80000	80100	80000	400535	1843720	0	2	40113	40109	40150	30051	3	30077	160100	200	80000	200	160000	40168	40110	1	1	80201	100	99	100	100	80000	80000	100	82490	16	1905	2470	2	2483	80046	1496	2	2518	754	4634	82506	31	1787	0	0	0	5110	1	16	1	1	40161	80002	80000	80100	40201	40155	40148	40126	40112
80204	40129	300	3	0	3	0	0	9999	79	2352	1	0	0	1400	12	112	40151	2310	743	617	48	25	160102	80102	80000	80100	80000	400535	1843576	0	2	40116	40146	40116	30053	3	30153	160100	200	80000	200	160000	40119	40107	1	1	80201	100	99	100	100	80000	80000	100	82494	18	1632	2467	3	2499	80026	1485	0	2508	974	4564	82500	50	1847	0	6	0	5110	1	16	1	1	40146	80002	80000	80100	40145	40172	40116	40131	40121
80204	40117	301	3	1	1	0	0	10041	43	2339	1	0	0	1488	8	116	40129	2291	512	576	47	25	160102	80102	80000	80100	80000	400535	1842520	1	2	40121	40150	40134	30050	3	30094	160100	200	80000	200	160000	40129	40121	1	1	80201	100	99	100	100	80000	80000	100	82510	21	2016	2470	0	2488	80046	1523	2	2488	994	4585	82497	26	1253	0	0	0	5110	1	16	1	1	40142	80002	80000	80100	40107	40148	40075	40117	40106
80204	40082	301	2	2	2	0	0	10269	32	2345	1	0	0	1256	11	496	40104	2268	577	606	938	278	162182	81566	80780	81583	81296	407382	1897384	1	2	41312	40663	41308	31054	29	31167	162088	202	80966	202	162640	41336	41432	10	1	80201	100	99	100	100	80000	80000	100	83062	16	2096	2421	302	2476	80653	1535	0	2467	986	11758	83121	33	1429	0	0	0	5308	1	65	1	1	41318	81024	80000	80100	41316	41256	41465	41460	41099
80204	41473	311	2	0	1	11	10	10764	866	2356	1	0	0	1664	11	168	41424	2311	775	454	817	238	162002	81326	80480	81230	81296	406196	1892776	0	2	41277	41487	41469	30971	44	31316	162528	206	81206	206	162424	41539	40955	11	1	80201	100	99	100	100	80000	80000	100	83105	8	1476	2439	310	2454	80641	1533	0	2488	346	12051	83097	27	1390	13	0	0	5254	1	16	1	1	40185	80002	80000	80100	40087	40102	40125	40147	40155
80204	40177	301	2	1	1	0	0	9939	34	2337	1	0	0	1496	8	252	40110	2303	459	585	40	25	160102	80102	80000	80100	80000	400535	1841752	1	2	40112	40130	40126	30055	3	30103	160100	200	80000	200	160000	40138	40094	1	1	80201	100	99	100	100	80000	80000	100	82486	16	1804	2469	9	2500	80033	1537	4	2500	896	4556	82512	26	1706	0	0	0	5110	1	16	1	1	40115	80002	80000	80100	40093	40117	40108	40088	40133
80204	40114	300	1	0	1	0	0	9978	45	2405	1	0	0	1032	7	204	40075	2279	518	691	46	25	160102	80102	80000	80100	80000	400535	1845160	1	2	40112	40137	40198	30029	3	30102	160100	200	80000	200	160000	40146	40131	1	1	80201	100	99	100	100	80000	80000	100	82488	16	1843	2448	13	2479	80036	1514	2	2500	1034	4603	82505	29	2206	0	0	0	5110	1	16	1	1	40128	80002	80000	80100	40122	40138	40124	40165	40129
80204	40114	301	2	2	2	0	0	10248	46	2377	1	0	0	1256	14	220	40134	2257	607	875	73	25	160102	80102	80000	80100	80000	400535	1845832	0	2	40128	40174	40112	30016	3	30072	160100	200	80000	200	160000	40144	40125	1	1	80201	100	99	100	100	80000	80000	100	82474	8	1960	2484	8	2496	80029	1532	0	2492	748	4539	82511	41	1545	0	0	0	5110	1	16	1	1	40135	80002	80000	80100	40137	40114	40177	40126	40147

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5015

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80034	40126	301	6	0	2	0	0	0	0	10041	38	2344	1	1240	15	152	40125	2283	575	595	23	25	160012	80012	80000	80010	80000	400087	1843096	1	0	2	40082	40109	40115	30046	3	30100	160010	20	80000	20	160000	40142	40120	1	1	80021	10	9	10	10	80000	80000	10	82502	20	1918	2474	11	2506	80036	1514	0	2516	1028	4683	82504	37	2385	0	3	0	5020	0	0	6	17	0	3	5	40135	80002	80000	80010	40115	40127	40166	40134	40137
80024	40086	301	4	0	0	0	0	0	0	10008	30	2380	1	1168	10	276	40103	2307	809	705	47	25	160012	80012	80000	80010	80000	400087	1843768	0	0	2	40107	40172	40112	30050	3	30084	160010	20	80000	20	160000	40133	40099	1	1	80021	10	9	10	10	80000	80000	10	82508	27	2153	2452	14	2498	80016	1520	0	2506	1226	4682	82504	22	1377	0	0	0	5020	0	0	5	16	0	6	5	40109	80002	80000	80010	40185	40147	40161	40143	40112
80024	40126	301	4	0	0	0	2	0	0	10047	26	2367	1	1440	11	516	40124	2284	791	654	35	25	160012	80012	80000	80010	80000	400087	1842136	0	0	2	40100	40134	40105	30037	3	30104	160010	20	80000	20	160000	40080	40105	1	1	80021	10	9	10	10	80000	80000	10	82502	10	1608	2457	2	2485	80025	1489	0	2498	1068	4535	82487	44	1713	0	4	0	5020	0	0	3	17	0	5	3	40116	80002	80000	80010	40188	40106	40089	40130	40152
80024	40093	300	5	0	3	0	3	0	0	10029	45	2365	4	1256	15	128	40091	2348	554	641	21	25	160012	80012	80000	80010	80000	400087	1843528	0	0	2	40142	40151	40128	30061	3	30132	160010	20	80000	20	160000	40177	40115	1	1	80021	10	9	10	10	80000	80000	10	82493	33	1712	2442	16	2486	80044	1508	0	2502	804	4556	82498	25	2224	0	4	0	5020	0	0	5	16	0	3	5	40147	80002	80000	80010	40143	40162	40131	40106	40133
80024	40139	301	6	0	0	0	4	0	0	10212	50	2351	1	1256	16	100	40135	2303	661	869	52	25	160012	80012	80000	80010	80000	400087	1846816	0	0	2	40153	40149	40163	30113	3	30138	160010	20	80000	20	160000	40112	40141	1	1	80021	10	9	10	10	80000	80000	10	82502	27	1462	2463	8	2491	80037	1537	0	2500	1002	4647	82506	37	2202	0	9	0	5020	0	0	5	16	0	3	5	40133	80002	80000	80010	40172	40184	40146	40195	40140
80024	40120	301	7	1	3	0	0	0	0	10086	50	2342	1	1440	18	236	40075	2300	649	763	53	25	160012	80012	80000	80010	80000	400087	1845832	0	0	2	40094	40147	40122	30074	3	30105	160010	20	80000	20	160000	40132	40128	1	1	80021	10	9	10	10	80000	80000	10	82496	20	1305	2466	3	2500	80020	1505	0	2482	1182	4622	82483	42	1443	0	0	0	5020	0	0	3	16	0	5	3	40139	80002	80000	80010	40143	40125	40126	40128	40158
80024	40094	301	5	0	2	0	0	0	0	10119	36	2387	1	1480	11	352	40078	2294	637	699	33	25	160012	80012	80000	80010	80000	400087	1845160	0	0	2	40125	40100	40159	30064	3	30088	160010	20	80000	20	160000	40124	40158	1	1	80021	10	9	10	10	80000	80000	10	82483	16	1956	2449	1	2503	80037	1546	2	2500	1222	4590	82480	18	1136	0	0	0	5020	0	0	6	16	0	3	5	40097	80002	80000	80010	40120	40157	40128	40185	40161
80024	40125	300	4	0	2	0	2	0	0	10074	27	2337	1	1248	11	212	40082	2317	743	697	35	25	160012	80012	80000	80010	80000	400087	1844800	1	0	2	40087	40135	40083	30084	3	30121	160010	20	80000	20	160000	40106	40124	1	1	80021	10	9	10	10	80000	80000	10	82498	9	1414	2470	8	2495	80030	1485	0	2500	766	4665	82514	38	1096	0	2	0	5020	0	0	6	17	0	3	5	40140	80002	80000	80010	40103	40151	40157	40098	40139
80024	40175	301	3	0	1	0	1	0	0	10062	45	2342	1	1424	5	172	40101	2244	556	473	51	25	160012	80012	80000	80010	80000	400087	1842832	1	0	2	40110	40096	40103	30094	3	30090	160010	20	80000	20	160000	40149	40190	1	1	80021	10	9	10	10	80000	80000	10	82490	9	1987	2483	11	2493	80019	1525	0	2498	1002	4556	82507	22	1484	0	0	0	5020	0	0	3	17	0	5	4	40133	80002	80000	80010	40096	40117	40120	40111	40114
80024	40103	300	3	0	0	0	0	0	0	10332	62	2316	1	1264	10	396	40131	2299	511	438	65	25	160012	80012	80000	80010	80000	400087	1843912	0	0	2	40079	40109	40124	30024	3	30158	160010	20	80000	20	160000	40120	40129	1	1	80021	10	9	10	10	80000	80000	10	82490	9	1545	2472	20	2492	80036	1557	1	2512	814	4590	82515	34	1859	0	0	0	5020	0	0	5	17	0	3	5	40097	80002	80000	80010	40101	40076	40104	40112	40096

STR (post-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations