Firestorm: STR (pre-index, D) measurements

Code:

  str d0, [x6, #0x10]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	1	1	1	0	12	32	1	13	0	1025	7	1	3	5	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1040	9	35	3	22	1007	0	2	50	16	7	1016	7	27	7	0	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	9	16	1	19	0	1025	8	3	4	4	25	2000	1000	1000	1000	1000	50762	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1017	19	15	2	26	1008	0	0	12	0	7	1000	7	23	7	1	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	9	16	1	19	0	1025	8	3	1	4	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1020	9	27	1	17	1007	0	1	24	8	10	1024	7	15	7	2	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	0	0	0	9	0	0	12	0	1025	8	2	2	5	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1034	9	39	5	10	1010	1	1	46	18	7	1016	7	19	7	2	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	9	16	2	7	0	1025	8	3	1	5	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1024	7	39	3	26	1007	0	2	24	16	10	1016	7	23	7	2	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	9	16	1	14	0	1025	5	1	3	3	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1019	7	11	0	25	1007	0	1	26	16	10	1016	7	23	7	3	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	0	9	0	0	14	0	1025	6	1	0	5	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1034	8	23	3	37	1011	0	1	17	16	7	1000	7	23	7	1	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	9	16	1	13	0	1025	8	3	0	3	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1025	8	23	2	9	1007	0	1	28	22	7	1018	7	31	7	1	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	0	0	9	16	1	14	0	1025	7	3	3	4	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1023	8	19	3	36	1007	0	2	26	18	7	1016	7	35	7	2	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	1	0	10	16	1	14	0	1025	8	2	2	4	25	2000	1000	1000	1000	1000	50754	45824	1015	1040	1040	824	3	898	2000	1000	2000	1040	1040	1	1	1001	1000	1000	1024	8	19	3	17	1010	0	0	24	18	7	1018	7	43	7	0	73	2	16	2	2	1037	1000	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 3->3

Code:

  str d0, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10214	10040	75	0	0	0	0	0	0	10509	83	2256	1	1632	3	0	732	10025	2244	0	238	215	25	25	20100	10100	10000	10100	10000	522165	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12477	0	1697	1482	0	1482	10994	1491	0	2461	50	4587	12513	30	690	0	710	1	17	1	1	10037	10000	343	1	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	0	0	10428	61	2308	1	1488	1	0	944	10025	2240	0	179	251	40	25	20100	10100	10000	10100	10000	522151	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12469	0	1592	1491	0	1556	11008	1498	0	2505	50	4597	12504	29	681	0	710	1	17	1	1	10037	10000	226	8	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	1	0	0	0	0	10293	76	2301	1	1632	2	1	944	10025	2284	0	243	206	28	25	20100	10100	10000	10100	10000	522173	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12473	0	1625	1487	0	1528	10977	1480	0	2497	50	4565	12519	28	787	0	710	1	17	1	1	10037	10000	141	4	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	0	0	10443	56	2270	1	1496	3	0	840	10025	2240	0	214	252	27	25	20100	10100	10000	10100	10000	522157	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12473	0	1614	1463	0	1467	10996	1498	0	2485	50	4558	12512	34	667	0	710	1	17	1	1	10037	10000	391	4	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	0	0	10380	44	2301	1	1712	2	0	780	10025	2267	0	240	239	32	25	20100	10100	10000	10100	10000	522165	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	0	1641	1521	0	1511	11017	1492	0	2497	50	4530	12518	27	654	0	710	1	17	1	1	10037	10000	149	2	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	0	0	0	0	0	0	10293	43	2263	1	1664	3	0	944	10025	2227	0	183	205	14	25	20100	10100	10000	10100	10000	522141	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	0	1585	1497	0	1479	11052	1506	0	2481	50	4505	12512	33	693	3	726	1	17	1	1	10037	10000	174	6	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	1	0	0	10608	62	2268	1	1704	6	8	724	10025	2243	0	211	179	37	25	20100	10100	10000	10100	10000	522125	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12464	4	1650	1496	0	1505	10960	1492	0	2473	50	4509	12506	32	689	1	710	1	17	1	1	10037	10000	246	3	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	1	0	0	0	10446	51	2261	1	1696	6	0	712	10025	2229	0	197	186	23	25	20100	10100	10000	10100	10000	522157	468824	1	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12481	4	1604	1494	0	1519	10980	1504	0	2497	50	4561	12502	22	683	1	710	1	17	1	1	10037	10000	279	7	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	0	0	0	0	10410	51	2275	1	1720	4	0	716	10025	2229	0	207	236	29	25	20100	10100	10000	10100	10000	522157	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12477	4	1681	1494	0	1540	11023	1507	0	2493	50	4638	12509	31	616	0	710	1	17	1	1	10037	10000	385	5	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	1	0	0	10476	40	2282	1	1712	4	2	724	10025	2243	0	215	204	27	25	20100	10100	10000	10100	10000	522133	468824	0	10017	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	10040	1	1	10201	100	99	100	100	10000	10000	100	12485	4	1521	1475	0	1531	11018	1510	0	2481	50	4598	12511	30	648	0	710	1	17	1	1	10037	10000	312	10	1	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	44	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10034	10040	76	2	2	0	2	10245	70	2264	1	1488	15	0	936	10025	2267	0	272	256	37	25	20010	10010	10000	10010	10000	521097	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12477	18	1604	1546	4	1576	10964	1546	2	2481	50	4541	12490	44	778	0	0	640	5	16	5	5	10037	10000	421	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	2	0	2	10200	70	2267	1	1616	11	0	720	10025	2239	0	257	242	48	25	20010	10010	10000	10010	10000	521073	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12497	18	1709	1529	4	1572	10936	1522	0	2501	50	4675	12495	30	741	7	3	640	5	16	4	5	10037	10000	293	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	3	0	10086	81	2302	1	1496	6	0	720	10025	2216	0	259	234	35	25	20010	10010	10000	10010	10000	521137	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12479	15	1627	1539	9	1565	10945	1502	0	2465	50	4536	12487	35	790	0	2	640	6	16	3	5	10037	10000	285	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	2	0	0	10155	95	2295	1	1544	8	0	760	10025	2218	0	229	208	63	25	20010	10010	10000	10010	10000	521065	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12493	16	1669	1538	0	1565	10924	1501	0	2485	50	4626	12496	33	740	0	0	640	5	16	5	5	10037	10000	299	2	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	1	0	0	1	10230	68	2305	1	1504	11	0	880	10025	2208	0	250	231	30	25	20010	10010	10000	10010	10000	520809	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12496	24	1536	1517	0	1540	10938	1529	0	2466	50	4529	12494	46	748	0	1	640	4	16	4	4	10037	10000	195	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	1	0	10338	98	2275	1	1712	11	0	724	10025	2236	0	244	263	58	25	20010	10010	10000	10010	10000	521105	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12480	16	1510	1557	3	1567	10968	1536	4	2465	50	4599	12500	45	698	14	0	640	3	16	5	5	10037	10000	352	2	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	0	3	10275	67	2268	1	1696	2	0	716	10025	2208	0	213	206	52	25	20010	10010	10000	10010	10000	521001	468824	0	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12504	21	1595	1531	0	1532	10944	1512	6	2478	50	4564	12516	51	705	0	2	640	5	16	4	3	10037	10000	272	9	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	0	0	0	10209	76	2243	1	1704	8	0	716	10025	2213	0	187	188	35	25	20010	10010	10000	10010	10000	521065	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12475	11	1540	1559	0	1560	10957	1520	0	2481	50	4576	12493	34	754	14	3	640	4	16	5	4	10037	10000	206	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	3	3	0	2	10182	53	2261	1	1712	12	0	724	10025	2229	0	240	211	32	25	20010	10010	10000	10010	10000	521041	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12495	20	1551	1568	2	1608	10971	1549	0	2470	50	4652	12500	37	795	7	0	640	4	16	4	4	10037	10000	221	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2	2	0	0	10194	68	2265	1	1704	10	0	724	10025	2235	0	239	255	40	25	20010	10010	10000	10010	10000	521089	468824	1	10022	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	10040	1	1	10021	10	9	10	10	10000	10000	10	12481	19	1581	1540	0	1589	10947	1543	0	2481	50	4600	12505	35	677	7	0	640	4	16	3	4	10037	10000	251	6	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  str d0, [x6, #0x10]!
  str d0, [x7, #0x10]!
  str d0, [x8, #0x10]!
  str d0, [x9, #0x10]!
  str d0, [x10, #0x10]!
  str d0, [x11, #0x10]!
  str d0, [x12, #0x10]!
  str d0, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5018

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80214	40155	300	3	0	0	0	0	10485	40	2246	1	1960	4	264	40126	2205	350	489	94	25	160102	80102	80000	80100	80000	400531	1844012	0	2	40177	40144	40159	30102	3	30116	160100	200	80000	200	160000	40146	40125	1	1	80201	100	99	100	100	80000	80000	100	82506	32	1615	2469	7	2500	80038	1528	0	2508	254	4592	82510	43	2344	14	0	0	5110	2	16	2	2	40109	80002	80000	80100	40199	40140	40130	40110	40172
80204	40112	301	5	0	5	0	0	10401	135	2231	1	1968	10	264	40151	2219	807	724	49	25	160102	80102	80000	80100	80000	400531	1843628	0	2	40127	40150	40118	30082	3	30108	160100	200	80000	200	160000	40135	40175	1	1	80201	100	99	100	100	80000	80000	100	82511	36	1779	2449	18	2457	80054	1508	0	2484	254	4636	82511	59	1800	14	5	0	5110	2	16	2	2	40201	80002	80000	80100	40234	40185	40210	40212	40175
80204	40176	300	5	0	0	0	0	10272	96	2246	1	1952	9	264	40132	2212	633	773	57	25	160102	80102	80000	80100	80000	400531	1845044	1	2	40140	40160	40183	30082	3	30158	160100	200	80000	200	160000	40178	40195	1	1	80201	100	99	100	100	80000	80000	100	82511	41	1851	2443	5	2477	80062	1510	5	2484	252	4607	82509	79	1961	14	0	0	5110	2	16	2	2	40151	80002	80000	80100	40140	40138	40138	40108	40174
80204	40164	301	6	0	0	0	0	10431	57	2260	1	1952	15	264	40176	2219	877	990	282	261	162023	81233	80710	81108	81080	405642	1891888	1	2	41203	41454	41372	30972	44	31137	162096	202	81218	200	161692	41415	41420	10	1	80201	100	99	100	100	80000	80000	100	82853	26	2516	2405	261	2461	80601	1544	0	2498	254	12249	83052	27	1684	0	0	0	5284	2	96	2	2	41013	81122	80000	80100	41353	41474	41504	40649	41408
80204	41467	311	3	0	0	10	10	11532	969	2241	1	1696	9	520	41566	2237	926	1025	804	219	161501	81230	80660	81260	81188	403376	1866124	1	2	40503	41503	41451	31075	44	31296	162307	202	81218	200	161452	41444	41573	11	1	80201	100	99	100	100	80000	80000	100	83153	24	1691	2441	310	2456	80329	1551	0	2472	92	12936	82758	71	1860	0	0	0	5304	2	16	2	2	40162	80002	80000	80100	40215	40161	40143	40139	40143
80204	40142	301	3	3	3	0	0	10383	43	2284	1	1672	13	568	40100	2249	861	694	85	25	160102	80102	80000	80100	80000	400535	1846360	1	2	40147	40138	40171	30072	3	30113	160100	200	80000	200	160000	40122	40161	1	1	80201	100	99	100	100	80000	80000	100	82487	18	1676	2463	14	2478	80038	1503	0	2484	254	4699	82512	53	1655	0	6	0	5110	2	16	2	2	40147	80002	80000	80100	40111	40184	40120	40146	40096
80204	40119	301	3	3	3	0	0	10392	47	2270	1	1712	9	520	40098	2251	560	917	50	25	160102	80102	80000	80100	80000	400535	1843888	1	2	40102	40161	40102	30038	3	30076	160100	200	80000	200	160000	40163	40138	1	1	80201	100	99	100	100	80000	80000	100	82471	30	2118	2426	6	2483	80043	1523	0	2476	254	4577	82513	41	1621	0	0	0	5110	2	16	2	2	40139	80002	80000	80100	40157	40132	40191	40133	40133
80204	40109	301	3	0	0	0	0	10497	36	2284	1	1712	6	500	40172	2244	573	721	61	25	160102	80102	80000	80100	80000	400535	1845472	1	2	40158	40133	40152	30038	3	30085	160100	200	80000	200	160000	40087	40136	1	1	80201	100	99	100	100	80000	80000	100	82492	35	2501	2434	8	2508	80042	1527	0	2507	254	4639	82503	43	2291	0	0	0	5110	2	16	2	2	40154	80002	80000	80100	40171	40148	40106	40159	40149
80204	40101	300	5	0	0	0	0	10551	70	2239	1	1952	13	264	40124	2212	633	660	53	25	160102	80102	80000	80100	80000	400535	1845256	1	2	40144	40152	40122	30191	3	30090	160100	200	80000	200	160000	40181	40144	1	1	80201	100	99	100	100	80000	80000	100	82497	35	1829	2421	10	2485	80040	1516	5	2468	252	4570	82505	48	1867	14	0	0	5110	2	16	2	2	40114	80002	80000	80100	40169	40161	40190	40162	40135
80204	40129	300	5	0	0	0	0	10452	61	2239	1	1968	14	264	40109	2218	825	855	48	25	160102	80102	80000	80100	80000	400535	1843384	1	2	40168	40167	40278	30057	3	30085	160100	200	80000	200	160000	40131	40109	1	1	80201	100	99	100	100	80000	80000	100	82500	28	2207	2431	5	2460	80049	1522	4	2492	254	4615	82512	46	1613	0	0	0	5110	2	16	2	2	40128	80002	80000	80100	40182	40123	40155	40142	40134

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5024

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80034	40162	300	1	0	1	1	0	0	10047	45	2297	1	0	0	1448	5	100	40137	2259	405	543	33	25	160012	80012	80000	80010	80000	400087	1844104	0	1	2	40112	40096	40132	30121	3	30087	160010	20	80000	20	160000	40133	40119	1	1	80021	10	9	10	10	80000	80000	10	82480	0	1300	2462	5	2494	80035	1518	0	2504	986	4547	82503	21	1093	0	0	5020	8	17	4	2	40171	80002	80000	80010	40091	40104	40124	40138	40109
80024	40103	301	0	0	0	0	0	0	10008	38	2289	1	0	0	1248	7	224	40075	2272	416	552	57	46	160012	80012	80000	80010	80108	400647	1846900	0	1	2	40092	40148	40101	30094	3	30090	160010	20	80000	20	160000	40120	40109	1	1	80021	10	9	10	10	80000	80000	10	82486	0	1995	2472	4	2485	80027	1518	0	2498	848	4521	82528	23	1182	0	0	5020	4	17	4	7	40117	80002	80000	80010	40162	40106	40079	40134	40150
80024	40131	300	0	0	0	0	0	0	9723	55	2329	2	0	0	1504	3	220	40090	2276	390	549	37	25	160012	80012	80000	80010	80000	400087	1843072	0	1	2	40093	40109	40147	30057	3	30120	160010	20	80000	20	160000	40147	40105	1	1	80021	10	9	10	10	80000	80000	10	82506	0	1011	2416	15	2477	80031	1521	0	2494	922	4586	82508	26	2205	0	1	5020	4	17	2	4	40133	80002	80000	80010	40150	40129	40129	40133	40077
80024	40112	300	0	1	0	0	0	0	9966	19	2299	1	0	0	1264	5	260	40098	2268	535	558	51	25	160012	80012	80000	80010	80000	400087	1847020	0	1	2	40101	40126	40154	30067	3	30069	160010	20	80000	20	160000	40111	40150	1	1	80021	10	9	10	10	80000	80000	10	83146	0	1306	2479	4	2480	80040	1516	0	2470	598	6831	83102	28	1525	0	0	5020	4	17	4	2	40134	80002	80000	80010	40176	40208	40249	40219	40191
80024	40300	301	1	1	0	0	0	0	10227	182	2292	0	1	0	1280	2	220	40240	2256	565	548	42	25	160012	80012	80000	80010	80000	400087	1850032	0	1	2	40280	40237	40358	30195	3	30128	160010	20	80000	20	160000	40285	40215	1	1	80021	10	9	10	10	80000	80000	10	82468	9	2264	2425	8	2470	80086	1536	0	2460	494	4709	82553	67	1750	0	1	5020	5	17	4	5	40244	80002	80000	80010	40149	40163	40163	40109	40167
80024	40102	301	1	1	0	1	0	0	10050	53	2312	0	1	0	1272	9	336	40230	2252	469	641	94	25	160012	80012	80000	80010	80000	400087	1848136	0	1	2	40151	40290	40228	30140	3	30241	160010	20	80000	20	160000	40171	40247	1	1	80021	10	9	10	10	80000	80000	10	82476	0	1544	2428	8	2427	80119	1505	0	2488	976	4742	82552	119	1928	0	0	5020	4	17	4	2	40244	80002	80000	80010	40286	40185	40182	40234	40161
80024	40212	302	1	1	1	0	0	0	9942	187	2292	0	1	0	1544	13	176	40115	2308	599	744	35	25	160012	80012	80000	80010	80000	400087	1876000	0	0	2	40120	40199	40162	30095	3	30102	160010	20	80000	20	160000	40186	40150	2	1	80021	10	9	10	10	80000	80000	10	82490	4	1696	2393	8	2482	80133	1517	0	2484	976	4672	82551	64	1611	0	0	5020	2	17	2	4	40224	80002	80000	80010	40250	40188	40217	40144	40168
80024	40197	302	0	2	0	0	0	0	10221	259	2300	0	1	0	1504	15	260	40163	2273	525	614	54	25	160012	80012	80000	80010	80000	400087	1846984	1	1	2	40171	40225	40269	30069	3	30221	160010	20	80000	20	160000	40278	40255	1	1	80021	10	9	10	10	80000	80000	10	82478	8	1993	2414	6	2461	80108	1523	0	2472	478	4749	82548	116	1024	0	0	5020	2	16	2	4	40264	80002	80000	80010	40246	40241	40164	40211	40131
80024	40177	313	1	1	1	0	0	0	9975	90	2267	0	0	1	1496	20	268	40175	2274	549	810	32	25	160012	80012	80000	80010	80000	400087	1847824	0	1	2	40221	40266	40213	30191	3	30183	160010	20	80000	20	160000	40161	40091	1	1	80021	10	9	10	10	80000	80000	10	82486	16	2382	2427	0	2479	80100	1513	0	2474	756	4761	82590	102	1810	0	4	5020	3	16	5	3	40275	80002	80000	80010	40245	40139	40198	40207	40261
80024	40198	301	2	0	0	0	0	0	9723	112	2309	0	0	1	1504	13	212	40230	2241	539	695	56	25	160012	80012	80000	80010	80000	400087	1852708	0	1	2	40264	40248	40220	30174	3	30219	160010	20	80000	20	160000	40235	40174	1	1	80021	10	9	10	10	80000	80000	10	82478	20	2454	2428	5	2507	80113	1501	4	2488	976	4635	82554	60	2059	0	0	5020	4	17	4	2	40151	80002	80000	80010	40256	40201	40517	40220	40219

STR (pre-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations