Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
str q0, [x6, #0x10]!
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 8 | 0 | 0 | 0 | 3 | 30 | 1 | 16 | 12 | 16 | 1025 | 8 | 1 | 1 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 0 | 19 | 2 | 43 | 1000 | 0 | 36 | 22 | 0 | 1016 | 19 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 2 | 16 | 1 | 0 | 10 | 12 | 1025 | 0 | 1 | 1 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 0 | 15 | 1 | 9 | 1000 | 0 | 24 | 30 | 0 | 1016 | 11 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 1 | 0 | 2 | 16 | 1 | 0 | 13 | 0 | 1025 | 8 | 0 | 3 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 0 | 19 | 1 | 24 | 1004 | 0 | 28 | 22 | 3 | 1016 | 15 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1092 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 6 | 3 | 18 | 1 | 0 | 12 | 0 | 1025 | 8 | 0 | 3 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 0 | 19 | 3 | 28 | 1003 | 0 | 24 | 18 | 0 | 1024 | 15 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 5 | 24 | 1 | 0 | 18 | 0 | 1025 | 8 | 0 | 1 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 31 | 0 | 0 | 1000 | 0 | 0 | 0 | 0 | 1000 | 31 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 2 | 16 | 1 | 0 | 11 | 0 | 1025 | 8 | 2 | 1 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1028 | 0 | 23 | 3 | 12 | 1003 | 0 | 32 | 24 | 0 | 1016 | 23 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 4 | 16 | 1 | 0 | 12 | 0 | 1025 | 16 | 1 | 5 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 0 | 15 | 1 | 9 | 1000 | 0 | 25 | 16 | 0 | 1016 | 19 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 3 | 24 | 1 | 0 | 12 | 0 | 1025 | 8 | 1 | 0 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 0 | 27 | 2 | 46 | 1003 | 0 | 16 | 0 | 0 | 1024 | 19 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 2 | 18 | 1 | 0 | 12 | 0 | 1025 | 14 | 5 | 4 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 0 | 23 | 2 | 9 | 1000 | 0 | 16 | 0 | 0 | 1016 | 19 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 6 | 2 | 16 | 1 | 0 | 12 | 12 | 1025 | 0 | 1 | 1 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 0 | 27 | 1 | 28 | 1000 | 0 | 24 | 30 | 0 | 1016 | 15 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
str q0, [x6, #0x10]!
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c3 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10214 | 10040 | 75 | 5 | 5 | 0 | 10404 | 67 | 2321 | 1 | 1712 | 22 | 0 | 964 | 10025 | 2274 | 0 | 202 | 203 | 58 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522125 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12517 | 51 | 1755 | 1394 | 0 | 1522 | 11083 | 1508 | 0 | 2475 | 50 | 4655 | 12475 | 33 | 764 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 288 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 7 | 7 | 0 | 10332 | 72 | 2261 | 1 | 1464 | 18 | 1 | 972 | 10025 | 2281 | 0 | 225 | 180 | 29 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522007 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12498 | 43 | 1801 | 1434 | 0 | 1465 | 11024 | 1511 | 0 | 2494 | 50 | 4584 | 12477 | 32 | 2746 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 288 | 5 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 6 | 0 | 0 | 10374 | 65 | 2304 | 1 | 1464 | 20 | 0 | 960 | 10025 | 2260 | 4 | 236 | 192 | 36 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522165 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12498 | 46 | 1798 | 1430 | 0 | 1477 | 11099 | 1517 | 0 | 2482 | 50 | 4659 | 12487 | 38 | 858 | 7 | 6 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 244 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 6 | 6 | 0 | 10290 | 71 | 2297 | 1 | 1656 | 15 | 0 | 956 | 10025 | 2233 | 0 | 179 | 198 | 43 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522141 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12524 | 43 | 1857 | 1405 | 0 | 1446 | 11066 | 1492 | 6 | 2495 | 50 | 4588 | 12468 | 37 | 890 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 180 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 6 | 0 | 0 | 10398 | 86 | 2303 | 1 | 1664 | 19 | 1 | 764 | 10025 | 2253 | 0 | 188 | 195 | 42 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522149 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12500 | 46 | 1771 | 1394 | 0 | 1437 | 11075 | 1541 | 6 | 2482 | 50 | 4602 | 12468 | 38 | 835 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 295 | 4 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 76 | 6 | 6 | 0 | 10812 | 67 | 2297 | 1 | 1656 | 22 | 0 | 980 | 10025 | 2267 | 0 | 176 | 187 | 30 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522093 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12481 | 46 | 1810 | 1426 | 0 | 1499 | 11073 | 1491 | 12 | 2478 | 50 | 4685 | 12477 | 32 | 800 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 207 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 6 | 6 | 6 | 10320 | 78 | 2305 | 1 | 1944 | 19 | 1 | 780 | 10025 | 2268 | 0 | 212 | 195 | 36 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522109 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12491 | 48 | 1718 | 1427 | 0 | 1432 | 11064 | 1515 | 0 | 2491 | 50 | 4539 | 12479 | 30 | 670 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 339 | 4 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 7 | 0 | 0 | 10299 | 76 | 2290 | 1 | 1984 | 23 | 0 | 712 | 10025 | 2282 | 0 | 201 | 189 | 45 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522101 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12519 | 51 | 1820 | 1421 | 0 | 1531 | 11082 | 1522 | 7 | 2491 | 50 | 4527 | 12472 | 36 | 958 | 7 | 7 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 383 | 5 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 7 | 0 | 7 | 10347 | 67 | 2319 | 1 | 1984 | 25 | 0 | 980 | 10025 | 2229 | 0 | 209 | 160 | 28 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522117 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12504 | 46 | 1903 | 1424 | 0 | 1450 | 11042 | 1524 | 0 | 2495 | 50 | 4586 | 12474 | 37 | 735 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 187 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 7 | 7 | 7 | 10503 | 65 | 2281 | 1 | 1968 | 27 | 1 | 948 | 10025 | 2267 | 0 | 185 | 184 | 39 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522093 | 468824 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12501 | 46 | 1791 | 1465 | 0 | 1488 | 11102 | 1513 | 7 | 2487 | 50 | 4524 | 12468 | 31 | 805 | 7 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 163 | 5 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10034 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 10104 | 96 | 2282 | 1 | 1664 | 1 | 0 | 1024 | 10025 | 2214 | 0 | 226 | 252 | 40 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521089 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12465 | 0 | 1593 | 1546 | 0 | 1579 | 10940 | 1508 | 1 | 2473 | 50 | 4504 | 12526 | 39 | 793 | 0 | 0 | 640 | 3 | 16 | 4 | 3 | 10037 | 10000 | 491 | 7 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 10149 | 52 | 2340 | 1 | 1248 | 2 | 0 | 752 | 10025 | 2215 | 0 | 228 | 233 | 34 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521081 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12473 | 0 | 1606 | 1546 | 0 | 1551 | 10960 | 1506 | 0 | 2481 | 50 | 4591 | 12498 | 34 | 789 | 0 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 269 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 0 | 10224 | 92 | 2268 | 1 | 1664 | 6 | 0 | 724 | 10025 | 2222 | 0 | 232 | 292 | 30 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521121 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12501 | 0 | 1683 | 1557 | 0 | 1559 | 10939 | 1545 | 0 | 2489 | 50 | 4666 | 12503 | 46 | 661 | 0 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 243 | 4 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 10035 | 69 | 2252 | 1 | 1472 | 1 | 0 | 948 | 10025 | 2223 | 0 | 245 | 243 | 29 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521065 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12474 | 4 | 1625 | 1537 | 0 | 1586 | 10954 | 1524 | 0 | 2493 | 50 | 4616 | 12529 | 46 | 755 | 0 | 1 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 368 | 6 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 10179 | 77 | 2253 | 1 | 1440 | 2 | 0 | 1188 | 10025 | 2226 | 0 | 201 | 276 | 28 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521137 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12482 | 4 | 1578 | 1560 | 0 | 1574 | 10933 | 1501 | 1 | 2481 | 50 | 4557 | 12504 | 34 | 871 | 0 | 0 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 254 | 2 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 0 | 0 | 10215 | 55 | 2235 | 1 | 1704 | 6 | 0 | 724 | 10025 | 2221 | 0 | 264 | 220 | 42 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521049 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12473 | 0 | 1546 | 1541 | 0 | 1580 | 10934 | 1519 | 0 | 2497 | 50 | 4592 | 12519 | 29 | 755 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 404 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 1 | 0 | 0 | 0 | 0 | 10341 | 79 | 2257 | 1 | 1664 | 0 | 0 | 724 | 10025 | 2216 | 0 | 209 | 245 | 41 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521121 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12501 | 0 | 1763 | 1567 | 3 | 1585 | 10934 | 1533 | 0 | 2477 | 50 | 4665 | 12509 | 39 | 662 | 0 | 1 | 672 | 5 | 25 | 4 | 4 | 10115 | 10000 | 294 | 3 | 0 | 10000 | 10010 | 10041 | 10091 | 10192 | 10093 | 10091 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 10563 | 75 | 2253 | 1 | 1752 | 1 | 0 | 704 | 10077 | 2125 | 0 | 249 | 303 | 33 | 46 | 20116 | 10038 | 10026 | 10156 | 10069 | 521081 | 471018 | 10022 | 10148 | 10113 | 8696 | 3 | 8835 | 20153 | 20 | 10000 | 20 | 20160 | 10040 | 10191 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12503 | 0 | 1587 | 1555 | 0 | 1579 | 10901 | 1471 | 0 | 2473 | 50 | 4638 | 12502 | 40 | 691 | 0 | 4 | 640 | 4 | 16 | 4 | 4 | 10037 | 10000 | 372 | 5 | 4 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 0 | 0 | 10704 | 51 | 2255 | 1 | 1624 | 6 | 0 | 724 | 10025 | 2220 | 0 | 217 | 242 | 44 | 25 | 20010 | 10010 | 10000 | 10010 | 10069 | 519533 | 468824 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10160 | 20 | 20320 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12503 | 8 | 1608 | 1525 | 0 | 1577 | 10960 | 1528 | 0 | 2501 | 50 | 4580 | 12507 | 37 | 714 | 0 | 4 | 640 | 4 | 16 | 3 | 3 | 10037 | 10000 | 331 | 11 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 81 | 1 | 2 | 0 | 0 | 0 | 10266 | 62 | 2248 | 1 | 1704 | 11 | 0 | 1432 | 10125 | 2222 | 0 | 255 | 302 | 131 | 126 | 20118 | 10066 | 10076 | 10161 | 10208 | 517537 | 473156 | 10141 | 10279 | 10343 | 8750 | 15 | 8770 | 20443 | 20 | 10080 | 20 | 20480 | 10141 | 10192 | 4 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12479 | 7 | 1676 | 1539 | 0 | 1542 | 10899 | 1511 | 0 | 2453 | 50 | 6766 | 12500 | 23 | 673 | 0 | 0 | 687 | 7 | 57 | 4 | 4 | 10115 | 10027 | 255 | 5 | 0 | 10000 | 10010 | 10191 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
str q0, [x6, #0x10]! str q0, [x7, #0x10]! str q0, [x8, #0x10]! str q0, [x9, #0x10]! str q0, [x10, #0x10]! str q0, [x11, #0x10]! str q0, [x12, #0x10]! str q0, [x13, #0x10]!
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5021
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80214 | 40182 | 301 | 4 | 0 | 4 | 10236 | 34 | 2246 | 1 | 1944 | 14 | 264 | 40154 | 2219 | 634 | 773 | 54 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1843072 | 1 | 2 | 40154 | 0 | 40148 | 40200 | 30084 | 3 | 30115 | 160100 | 200 | 80000 | 200 | 160000 | 40164 | 40104 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82492 | 26 | 2147 | 2438 | 6 | 2478 | 80050 | 1526 | 0 | 2492 | 254 | 4624 | 82501 | 55 | 3092 | 14 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40239 | 80002 | 80000 | 80100 | 40155 | 40167 | 40175 | 40191 | 40143 |
| 80204 | 40128 | 301 | 5 | 0 | 0 | 9948 | 66 | 2264 | 1 | 1704 | 10 | 520 | 40147 | 2333 | 589 | 883 | 57 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400531 | 1844660 | 1 | 2 | 40098 | 0 | 40113 | 40189 | 30041 | 3 | 30190 | 160100 | 200 | 80000 | 200 | 160000 | 40168 | 40188 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82506 | 34 | 2053 | 2413 | 12 | 2475 | 80106 | 1534 | 0 | 2484 | 254 | 4638 | 82508 | 114 | 2354 | 14 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40173 | 80002 | 80000 | 80100 | 40144 | 40200 | 40208 | 40207 | 40211 |
| 80204 | 40154 | 302 | 6 | 0 | 0 | 9927 | 30 | 2246 | 1 | 1952 | 9 | 264 | 40148 | 2212 | 574 | 754 | 36 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1843936 | 1 | 2 | 40132 | 0 | 40140 | 40180 | 30029 | 3 | 30161 | 160100 | 200 | 80000 | 200 | 160000 | 40128 | 40178 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82484 | 26 | 1407 | 2422 | 10 | 2471 | 80045 | 1557 | 0 | 2468 | 1164 | 4585 | 82490 | 30 | 2592 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40129 | 80002 | 80000 | 80100 | 40206 | 40188 | 40117 | 40180 | 40193 |
| 80204 | 40195 | 301 | 4 | 4 | 0 | 10170 | 63 | 2232 | 1 | 1968 | 6 | 264 | 40132 | 2198 | 507 | 722 | 52 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844248 | 0 | 2 | 40110 | 0 | 40140 | 40145 | 30065 | 3 | 30137 | 160100 | 200 | 80000 | 200 | 160000 | 40165 | 40145 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82479 | 14 | 1718 | 2422 | 6 | 2464 | 80049 | 1546 | 0 | 2484 | 254 | 4670 | 82505 | 18 | 2151 | 0 | 3 | 0 | 5110 | 1 | 16 | 1 | 1 | 40185 | 80002 | 80000 | 80100 | 40160 | 40311 | 40226 | 40218 | 40197 |
| 80204 | 40148 | 301 | 3 | 3 | 3 | 10143 | 40 | 2239 | 1 | 1944 | 7 | 264 | 40109 | 2191 | 446 | 676 | 70 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844248 | 0 | 2 | 40157 | 0 | 40150 | 40155 | 30088 | 3 | 30064 | 160100 | 200 | 80000 | 200 | 160000 | 40137 | 40182 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82467 | 14 | 1859 | 2446 | 15 | 2465 | 80043 | 1520 | 0 | 2452 | 254 | 4561 | 82489 | 34 | 2228 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40155 | 80002 | 80000 | 80100 | 40201 | 40122 | 40107 | 40135 | 40188 |
| 80204 | 40149 | 300 | 4 | 0 | 0 | 10083 | 46 | 2278 | 1 | 1712 | 11 | 520 | 40144 | 2237 | 727 | 796 | 57 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1845400 | 0 | 2 | 40142 | 0 | 40174 | 40156 | 30082 | 3 | 30130 | 160100 | 200 | 80000 | 200 | 160000 | 40140 | 40133 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82492 | 14 | 1831 | 2436 | 7 | 2479 | 80049 | 1488 | 0 | 2492 | 254 | 4673 | 82488 | 27 | 1384 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40181 | 80002 | 80000 | 80100 | 40168 | 40124 | 40199 | 40178 | 40165 |
| 80204 | 40170 | 300 | 4 | 0 | 4 | 10068 | 70 | 2264 | 1 | 1720 | 10 | 520 | 40132 | 2251 | 630 | 695 | 47 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1842952 | 0 | 2 | 40100 | 0 | 40153 | 40184 | 30070 | 3 | 30128 | 160100 | 200 | 80000 | 200 | 160000 | 40141 | 40172 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82458 | 20 | 1219 | 2426 | 2 | 2461 | 80040 | 1495 | 3 | 2476 | 1074 | 4625 | 82510 | 29 | 1673 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40155 | 80002 | 80000 | 80100 | 40188 | 40127 | 40150 | 40145 | 40163 |
| 80204 | 40123 | 300 | 5 | 0 | 6 | 9981 | 37 | 2250 | 1 | 1704 | 12 | 520 | 40163 | 2251 | 673 | 628 | 51 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1845280 | 0 | 2 | 40097 | 0 | 40111 | 40137 | 30042 | 3 | 30128 | 160100 | 200 | 80000 | 200 | 160000 | 40151 | 40153 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82484 | 14 | 2182 | 2432 | 3 | 2491 | 80027 | 1502 | 6 | 2492 | 254 | 4641 | 82555 | 65 | 2325 | 0 | 3 | 0 | 5110 | 1 | 16 | 1 | 1 | 40152 | 80002 | 80000 | 80100 | 40214 | 40155 | 40161 | 40170 | 40129 |
| 80204 | 40131 | 301 | 3 | 3 | 0 | 9882 | 41 | 2257 | 1 | 1696 | 15 | 520 | 40108 | 2230 | 759 | 626 | 65 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1847800 | 0 | 2 | 40088 | 0 | 40116 | 40182 | 30050 | 3 | 30100 | 160100 | 200 | 80000 | 200 | 160000 | 40147 | 40173 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82492 | 22 | 2147 | 2409 | 11 | 2492 | 80032 | 1505 | 8 | 2500 | 254 | 4645 | 82488 | 35 | 2643 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40124 | 80002 | 80000 | 80100 | 40150 | 40165 | 40147 | 40247 | 40150 |
| 80204 | 40154 | 301 | 4 | 0 | 4 | 10287 | 47 | 2232 | 1 | 1976 | 15 | 264 | 40173 | 2191 | 715 | 777 | 69 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1845088 | 0 | 2 | 40146 | 0 | 40128 | 40168 | 30056 | 3 | 30147 | 160100 | 200 | 80000 | 200 | 160272 | 40135 | 40122 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82476 | 30 | 2662 | 2425 | 4 | 2446 | 80049 | 1554 | 5 | 2476 | 254 | 4596 | 82489 | 29 | 2649 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40197 | 80002 | 80000 | 80100 | 40215 | 40164 | 40213 | 40163 | 40180 |
Result (median cycles for code divided by count): 0.5015
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 24 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 61 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | branch mispred nonspec (cb) | cf | d0 | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80034 | 40102 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 10191 | 41 | 2299 | 1 | 0 | 1488 | 2 | 148 | 40123 | 2257 | 374 | 481 | 53 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1842472 | 0 | 2 | 40098 | 40113 | 40118 | 30068 | 3 | 30068 | 160010 | 20 | 80000 | 20 | 160000 | 40102 | 40129 | 1 | 1 | 80022 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82505 | 0 | 1127 | 2462 | 3 | 2484 | 80015 | 1528 | 0 | 2502 | 974 | 4591 | 82516 | 41 | 1701 | 2 | 0 | 5020 | 0 | 8 | 1 | 26 | 17 | 0 | 25 | 24 | 40092 | 80002 | 80000 | 80010 | 40117 | 40129 | 40099 | 40176 | 40094 |
| 80024 | 40096 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 10152 | 24 | 2299 | 1 | 0 | 1296 | 4 | 252 | 40110 | 2311 | 347 | 299 | 18 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1842424 | 0 | 2 | 40102 | 40108 | 40116 | 30068 | 3 | 30092 | 160010 | 20 | 80000 | 20 | 160000 | 40126 | 40144 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82494 | 0 | 1294 | 2480 | 3 | 2479 | 80036 | 1553 | 0 | 2505 | 796 | 4587 | 82530 | 30 | 934 | 0 | 0 | 5020 | 0 | 11 | 0 | 26 | 49 | 0 | 15 | 27 | 40394 | 80002 | 80000 | 80010 | 40110 | 40149 | 40146 | 40146 | 40108 |
| 80024 | 40123 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 10272 | 73 | 2305 | 1 | 0 | 1600 | 4 | 260 | 40134 | 2360 | 427 | 490 | 24 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1842496 | 0 | 2 | 40123 | 40198 | 40097 | 30065 | 3 | 30136 | 160010 | 20 | 80000 | 20 | 160000 | 40101 | 40100 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82486 | 0 | 992 | 2464 | 12 | 2497 | 80048 | 1517 | 0 | 2494 | 976 | 4492 | 82526 | 37 | 1080 | 0 | 0 | 5020 | 0 | 8 | 0 | 10 | 17 | 0 | 25 | 15 | 40073 | 80002 | 80000 | 80010 | 40123 | 40120 | 40085 | 40141 | 40124 |
| 80024 | 40099 | 301 | 0 | 0 | 0 | 0 | 0 | 0 | 10065 | 34 | 2346 | 1 | 0 | 1480 | 3 | 112 | 40071 | 2307 | 423 | 543 | 78 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843456 | 0 | 2 | 40099 | 40129 | 40108 | 30051 | 3 | 30134 | 160010 | 20 | 80000 | 20 | 160000 | 40090 | 40069 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82487 | 0 | 1101 | 2468 | 0 | 2499 | 80020 | 1527 | 0 | 2478 | 884 | 4623 | 82519 | 27 | 1668 | 0 | 0 | 5020 | 0 | 7 | 0 | 22 | 17 | 0 | 26 | 26 | 40102 | 80002 | 80000 | 80010 | 40117 | 40104 | 40114 | 40112 | 40110 |
| 80024 | 40124 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 10287 | 51 | 2326 | 1 | 0 | 1512 | 6 | 232 | 40080 | 2310 | 608 | 467 | 34 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1841608 | 0 | 2 | 40041 | 40101 | 40109 | 30014 | 3 | 30200 | 160010 | 20 | 80000 | 20 | 160000 | 40094 | 40090 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82478 | 0 | 1901 | 2495 | 12 | 2492 | 80038 | 1519 | 0 | 2507 | 986 | 4439 | 82530 | 36 | 1337 | 0 | 0 | 5020 | 0 | 10 | 0 | 25 | 17 | 1 | 17 | 28 | 40096 | 80226 | 80000 | 80010 | 40125 | 40103 | 40130 | 40116 | 40173 |
| 80024 | 40153 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 10233 | 42 | 2348 | 1 | 0 | 1488 | 3 | 168 | 40098 | 2296 | 495 | 320 | 27 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1844440 | 0 | 2 | 40088 | 40097 | 40111 | 30037 | 3 | 30294 | 160010 | 20 | 80000 | 20 | 160000 | 40152 | 40100 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82464 | 0 | 1308 | 2472 | 7 | 2501 | 80041 | 1534 | 0 | 2494 | 756 | 4664 | 82521 | 20 | 1055 | 0 | 0 | 5020 | 0 | 7 | 0 | 16 | 17 | 0 | 15 | 27 | 40111 | 80002 | 80000 | 80010 | 40145 | 40098 | 40135 | 40091 | 40091 |
| 80024 | 40111 | 301 | 0 | 0 | 0 | 0 | 0 | 0 | 10122 | 40 | 2302 | 1 | 0 | 1384 | 3 | 324 | 40081 | 2273 | 520 | 364 | 31 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1843336 | 0 | 2 | 40133 | 40108 | 40122 | 30062 | 3 | 30150 | 160010 | 20 | 80000 | 20 | 160000 | 40127 | 40105 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82478 | 0 | 1417 | 2471 | 2 | 2506 | 80038 | 1492 | 0 | 2477 | 984 | 4675 | 82521 | 45 | 1659 | 0 | 0 | 5020 | 0 | 9 | 0 | 27 | 49 | 0 | 17 | 29 | 40152 | 80002 | 80000 | 80010 | 40108 | 40109 | 40115 | 40180 | 40089 |
| 80024 | 40102 | 300 | 0 | 0 | 0 | 0 | 1 | 0 | 9990 | 48 | 2308 | 1 | 0 | 1464 | 5 | 188 | 40071 | 2278 | 455 | 366 | 3 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1844248 | 0 | 2 | 40073 | 40116 | 40139 | 30036 | 3 | 30067 | 160010 | 20 | 80000 | 20 | 160000 | 40109 | 40113 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82500 | 0 | 1109 | 2465 | 4 | 2476 | 80032 | 1491 | 0 | 2507 | 846 | 4576 | 82511 | 20 | 1056 | 0 | 0 | 5020 | 0 | 6 | 0 | 23 | 17 | 0 | 28 | 27 | 40131 | 80002 | 80000 | 80010 | 40096 | 40098 | 40106 | 40106 | 40096 |
| 80024 | 40096 | 301 | 0 | 0 | 0 | 0 | 0 | 0 | 10245 | 51 | 2338 | 1 | 0 | 1520 | 5 | 280 | 40121 | 2298 | 561 | 511 | 4 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1841800 | 0 | 2 | 40103 | 40094 | 40085 | 30022 | 3 | 30084 | 160010 | 20 | 80000 | 20 | 160000 | 40104 | 40102 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82494 | 0 | 1510 | 2486 | 7 | 2500 | 80028 | 1476 | 0 | 2507 | 792 | 4569 | 82500 | 17 | 1331 | 0 | 0 | 5020 | 0 | 6 | 0 | 23 | 17 | 0 | 27 | 25 | 40094 | 80002 | 80000 | 80010 | 40131 | 40143 | 40106 | 40099 | 40106 |
| 80024 | 40105 | 300 | 0 | 0 | 0 | 0 | 0 | 0 | 10440 | 29 | 2300 | 1 | 0 | 1496 | 4 | 212 | 40082 | 2293 | 706 | 372 | 30 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400087 | 1844440 | 0 | 2 | 40087 | 40098 | 40131 | 30066 | 3 | 30091 | 160010 | 20 | 80000 | 20 | 160000 | 40120 | 40105 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82489 | 0 | 2122 | 2463 | 8 | 2476 | 80018 | 1490 | 0 | 2486 | 986 | 4517 | 82505 | 22 | 1639 | 0 | 0 | 5020 | 0 | 10 | 0 | 25 | 17 | 0 | 27 | 17 | 40156 | 80002 | 80000 | 80010 | 40120 | 40146 | 40139 | 40141 | 40090 |