Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
str s0, [x6, #0x10]!
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 8 | 1 | 1 | 1 | 1 | 6 | 13 | 32 | 1 | 0 | 8 | 12 | 1025 | 0 | 4 | 0 | 8 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1064 | 9 | 52 | 0 | 34 | 1009 | 0 | 2 | 12 | 0 | 7 | 1000 | 7 | 51 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 2 | 3 | 1 | 3 | 12 | 46 | 0 | 8 | 16 | 0 | 1025 | 34 | 0 | 0 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1009 | 9 | 31 | 0 | 0 | 1007 | 1 | 2 | 0 | 0 | 7 | 1000 | 7 | 31 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 1 | 1 | 0 | 12 | 42 | 1 | 0 | 10 | 44 | 1025 | 49 | 0 | 0 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1008 | 8 | 27 | 2 | 10 | 1010 | 0 | 1 | 52 | 14 | 7 | 1022 | 7 | 35 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 1 | 0 | 18 | 10 | 12 | 0 | 0 | 12 | 4 | 1025 | 24 | 0 | 0 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1064 | 8 | 43 | 2 | 19 | 1007 | 0 | 1 | 30 | 16 | 7 | 1008 | 7 | 47 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 2 | 3 | 1 | 9 | 12 | 35 | 0 | 0 | 9 | 4 | 1025 | 12 | 0 | 1 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 0 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1008 | 7 | 43 | 0 | 1 | 1007 | 0 | 1 | 0 | 14 | 7 | 1032 | 7 | 27 | 7 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 1 | 1 | 78 | 11 | 22 | 1 | 8 | 8 | 0 | 1025 | 0 | 1 | 3 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1040 | 7 | 47 | 7 | 42 | 1013 | 0 | 0 | 0 | 0 | 7 | 1032 | 7 | 31 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 1 | 96 | 12 | 56 | 0 | 0 | 2 | 0 | 1025 | 0 | 0 | 0 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1008 | 8 | 31 | 0 | 28 | 1017 | 0 | 1 | 0 | 14 | 7 | 1022 | 7 | 35 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 1 | 12 | 12 | 40 | 0 | 0 | 17 | 12 | 1025 | 35 | 0 | 1 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 0 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1064 | 7 | 39 | 4 | 43 | 1013 | 0 | 0 | 36 | 0 | 10 | 1032 | 7 | 51 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 2 | 27 | 10 | 49 | 0 | 0 | 2 | 36 | 1025 | 40 | 0 | 0 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1052 | 24 | 35 | 1 | 10 | 1009 | 0 | 2 | 0 | 0 | 7 | 1000 | 7 | 51 | 7 | 2 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 0 | 1 | 18 | 11 | 30 | 1 | 0 | 5 | 40 | 1025 | 10 | 1 | 2 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1015 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 2000 | 1040 | 1040 | 1 | 1 | 1001 | 1000 | 1000 | 1033 | 17 | 51 | 5 | 24 | 1007 | 0 | 1 | 36 | 24 | 7 | 1036 | 7 | 39 | 7 | 1 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 0 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
str s0, [x6, #0x10]!
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10214 | 10040 | 75 | 4 | 4 | 4 | 10353 | 75 | 2253 | 1 | 1712 | 20 | 0 | 724 | 10025 | 2228 | 165 | 208 | 36 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522153 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8681 | 6 | 8742 | 20106 | 200 | 10008 | 200 | 20016 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12495 | 39 | 1787 | 1432 | 0 | 1461 | 11030 | 1492 | 0 | 2493 | 50 | 4550 | 12469 | 21 | 767 | 0 | 0 | 1 | 1 | 1 | 717 | 0 | 0 | 0 | 16 | 0 | 0 | 10037 | 10000 | 275 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 5 | 5 | 0 | 10545 | 76 | 2275 | 1 | 1712 | 20 | 0 | 724 | 10025 | 2229 | 176 | 189 | 47 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 521917 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8681 | 7 | 8742 | 20106 | 200 | 10008 | 200 | 20016 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12481 | 34 | 1706 | 1443 | 0 | 1487 | 11009 | 1501 | 4 | 2497 | 50 | 4612 | 12494 | 26 | 754 | 0 | 4 | 1 | 1 | 1 | 718 | 0 | 0 | 0 | 16 | 0 | 0 | 10037 | 10000 | 350 | 7 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 5 | 0 | 0 | 10506 | 60 | 2294 | 1 | 1496 | 8 | 1 | 716 | 10025 | 2222 | 223 | 218 | 37 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522159 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8681 | 7 | 8743 | 20106 | 200 | 10008 | 200 | 20016 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12493 | 36 | 1713 | 1471 | 0 | 1501 | 11041 | 1535 | 0 | 2497 | 50 | 4490 | 12487 | 22 | 874 | 7 | 10 | 1 | 1 | 1 | 717 | 0 | 0 | 0 | 16 | 0 | 0 | 10037 | 10000 | 349 | 6 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 4 | 0 | 0 | 10449 | 62 | 2275 | 1 | 1720 | 12 | 1 | 716 | 10025 | 2234 | 179 | 195 | 34 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522183 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8681 | 6 | 8742 | 20106 | 200 | 10008 | 200 | 20016 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12479 | 24 | 1650 | 1471 | 0 | 1486 | 10987 | 1532 | 0 | 2489 | 50 | 4593 | 12494 | 25 | 842 | 0 | 0 | 1 | 1 | 1 | 718 | 0 | 0 | 0 | 16 | 0 | 0 | 10037 | 10000 | 220 | 2 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 4 | 4 | 0 | 10386 | 56 | 2306 | 1 | 1584 | 17 | 0 | 952 | 10025 | 2239 | 237 | 208 | 31 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522183 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8681 | 6 | 8742 | 20106 | 200 | 10008 | 200 | 20016 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12489 | 39 | 1756 | 1468 | 0 | 1507 | 11014 | 1525 | 0 | 2473 | 50 | 4671 | 12486 | 33 | 750 | 0 | 4 | 0 | 0 | 0 | 710 | 0 | 0 | 1 | 17 | 1 | 1 | 10037 | 10000 | 222 | 4 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 76 | 4 | 0 | 0 | 10410 | 93 | 2267 | 1 | 1704 | 17 | 1 | 724 | 10025 | 2243 | 177 | 219 | 48 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522039 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12513 | 31 | 1818 | 1445 | 0 | 1453 | 11145 | 1513 | 0 | 2481 | 50 | 4528 | 12474 | 22 | 758 | 0 | 0 | 0 | 0 | 0 | 710 | 0 | 0 | 1 | 17 | 1 | 1 | 10037 | 10000 | 255 | 4 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 4 | 0 | 4 | 10551 | 51 | 2276 | 1 | 1688 | 11 | 1 | 764 | 10025 | 2228 | 231 | 177 | 20 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522103 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12481 | 35 | 1735 | 1417 | 0 | 1504 | 11018 | 1558 | 5 | 2481 | 50 | 4494 | 12467 | 26 | 805 | 0 | 5 | 0 | 0 | 0 | 710 | 0 | 0 | 1 | 17 | 1 | 1 | 10037 | 10000 | 313 | 7 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 76 | 3 | 0 | 3 | 10230 | 74 | 2278 | 1 | 1696 | 15 | 0 | 932 | 10025 | 2242 | 177 | 222 | 26 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 521803 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12493 | 34 | 1718 | 1474 | 0 | 1511 | 11015 | 1503 | 0 | 2485 | 50 | 4469 | 12475 | 27 | 783 | 0 | 0 | 0 | 0 | 0 | 710 | 0 | 0 | 1 | 17 | 1 | 1 | 10037 | 10000 | 274 | 9 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 4 | 0 | 4 | 10317 | 65 | 2267 | 1 | 1696 | 11 | 0 | 724 | 10025 | 2217 | 199 | 177 | 40 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522165 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12489 | 24 | 1729 | 1440 | 0 | 1482 | 11021 | 1551 | 6 | 2493 | 50 | 4679 | 12481 | 59 | 755 | 0 | 6 | 0 | 0 | 0 | 710 | 0 | 0 | 1 | 17 | 1 | 1 | 10037 | 10000 | 220 | 1 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 4 | 4 | 0 | 10404 | 65 | 2308 | 1 | 1720 | 10 | 1 | 932 | 10025 | 2237 | 187 | 182 | 38 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522151 | 468824 | 0 | 0 | 10017 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 20000 | 10040 | 10040 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 10000 | 100 | 12481 | 35 | 1599 | 1496 | 0 | 1503 | 10996 | 1531 | 4 | 2481 | 50 | 4538 | 12488 | 30 | 772 | 0 | 0 | 0 | 0 | 0 | 710 | 0 | 0 | 1 | 17 | 1 | 1 | 10037 | 10000 | 257 | 3 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 44 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10034 | 10040 | 75 | 1 | 1 | 1 | 10134 | 74 | 2246 | 1 | 1720 | 8 | 2 | 704 | 10025 | 2222 | 0 | 269 | 223 | 37 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521065 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12477 | 0 | 1585 | 1555 | 1534 | 10977 | 1557 | 0 | 2473 | 50 | 4630 | 12498 | 31 | 700 | 0 | 0 | 640 | 4 | 16 | 3 | 3 | 10037 | 10000 | 336 | 12 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 10125 | 75 | 2260 | 1 | 1496 | 3 | 0 | 940 | 10025 | 2218 | 0 | 233 | 252 | 39 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521033 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12485 | 0 | 1573 | 1555 | 1546 | 10965 | 1516 | 0 | 2481 | 50 | 4570 | 12509 | 25 | 738 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 388 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 10182 | 71 | 2275 | 1 | 1664 | 3 | 0 | 912 | 10025 | 2233 | 0 | 223 | 268 | 37 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520593 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12469 | 8 | 1697 | 1534 | 1552 | 10944 | 1491 | 0 | 2481 | 50 | 4598 | 12494 | 37 | 779 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 291 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 10203 | 80 | 2272 | 1 | 1688 | 5 | 0 | 720 | 10025 | 2219 | 0 | 259 | 276 | 38 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521009 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12477 | 8 | 1672 | 1500 | 1570 | 10949 | 1522 | 0 | 2457 | 50 | 4576 | 12491 | 35 | 678 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 353 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 10254 | 53 | 2291 | 1 | 1656 | 7 | 0 | 708 | 10025 | 2259 | 0 | 252 | 235 | 41 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521089 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12473 | 8 | 1678 | 1548 | 1549 | 10948 | 1504 | 1 | 2473 | 50 | 4626 | 12523 | 32 | 740 | 0 | 0 | 640 | 2 | 16 | 3 | 2 | 10037 | 10000 | 260 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 10299 | 71 | 2264 | 1 | 1664 | 3 | 0 | 756 | 10025 | 2226 | 0 | 267 | 250 | 36 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520985 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12494 | 10 | 1657 | 1533 | 1560 | 10972 | 1506 | 1 | 2485 | 50 | 4707 | 12496 | 38 | 814 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 220 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 10116 | 66 | 2279 | 1 | 1576 | 3 | 1 | 936 | 10025 | 2236 | 0 | 226 | 222 | 31 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520785 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12481 | 8 | 1761 | 1555 | 1558 | 10961 | 1501 | 1 | 2473 | 50 | 4586 | 12513 | 36 | 600 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 196 | 6 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 0 | 0 | 0 | 10164 | 87 | 2268 | 1 | 1512 | 3 | 0 | 804 | 10025 | 2219 | 0 | 275 | 271 | 37 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 520897 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12481 | 10 | 1691 | 1579 | 1568 | 10966 | 1512 | 2 | 2473 | 50 | 4621 | 12510 | 34 | 826 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 10037 | 10000 | 305 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 0 | 10311 | 74 | 2246 | 1 | 1488 | 2 | 0 | 788 | 10025 | 2243 | 0 | 222 | 294 | 31 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521089 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12493 | 8 | 1720 | 1512 | 1598 | 10956 | 1515 | 0 | 2473 | 50 | 4545 | 12512 | 35 | 691 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 220 | 2 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 10116 | 71 | 2262 | 1 | 1496 | 4 | 0 | 716 | 10025 | 2226 | 0 | 260 | 249 | 39 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521145 | 468824 | 1 | 10022 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 20000 | 10040 | 10040 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10000 | 10 | 12474 | 10 | 1648 | 1548 | 1550 | 10958 | 1499 | 0 | 2477 | 50 | 4493 | 12500 | 43 | 681 | 0 | 0 | 640 | 3 | 16 | 3 | 2 | 10037 | 10000 | 382 | 3 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
str s0, [x6, #0x10]! str s0, [x7, #0x10]! str s0, [x8, #0x10]! str s0, [x9, #0x10]! str s0, [x10, #0x10]! str s0, [x11, #0x10]! str s0, [x12, #0x10]! str s0, [x13, #0x10]!
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5017
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 23 | 24 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c3 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80214 | 40167 | 300 | 1 | 0 | 0 | 0 | 0 | 0 | 10038 | 32 | 2295 | 1 | 0 | 0 | 1328 | 5 | 256 | 40118 | 2265 | 427 | 379 | 47 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1843648 | 1 | 2 | 40069 | 40102 | 40146 | 30083 | 3 | 30079 | 160100 | 200 | 80000 | 200 | 160000 | 40119 | 40136 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82476 | 0 | 1674 | 2463 | 9 | 2483 | 80034 | 1538 | 0 | 2474 | 986 | 4614 | 82520 | 34 | 1136 | 0 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 40157 | 80002 | 80000 | 80100 | 40138 | 40134 | 40154 | 40148 | 40208 |
| 80204 | 40101 | 301 | 1 | 1 | 0 | 0 | 0 | 0 | 10050 | 43 | 2265 | 1 | 0 | 0 | 1528 | 3 | 232 | 40095 | 2290 | 568 | 578 | 73 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844488 | 1 | 2 | 40133 | 40154 | 40188 | 30100 | 3 | 30087 | 160100 | 200 | 80000 | 200 | 160000 | 40175 | 40162 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82508 | 2 | 1447 | 2447 | 3 | 2476 | 80043 | 1515 | 2 | 2492 | 766 | 4552 | 82510 | 21 | 1928 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40117 | 80002 | 80000 | 80100 | 40158 | 40119 | 40169 | 40124 | 40139 |
| 80204 | 40146 | 301 | 1 | 0 | 1 | 0 | 0 | 0 | 10161 | 40 | 2304 | 1 | 0 | 0 | 1256 | 4 | 232 | 40133 | 2264 | 473 | 477 | 67 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844296 | 1 | 2 | 40087 | 40193 | 40166 | 30048 | 3 | 30108 | 160100 | 200 | 80000 | 200 | 160000 | 40127 | 40117 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82489 | 2 | 1538 | 2442 | 0 | 2482 | 80027 | 1502 | 0 | 2480 | 762 | 4568 | 82514 | 23 | 1433 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40111 | 80002 | 80000 | 80100 | 40169 | 40141 | 40161 | 40122 | 40124 |
| 80204 | 40121 | 301 | 1 | 1 | 0 | 0 | 0 | 0 | 9972 | 87 | 2283 | 1 | 0 | 0 | 1480 | 8 | 196 | 40137 | 2282 | 487 | 379 | 44 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844416 | 1 | 2 | 40138 | 40137 | 40151 | 30021 | 3 | 30128 | 160100 | 200 | 80000 | 200 | 160000 | 40184 | 40126 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82480 | 5 | 2101 | 2446 | 2 | 2464 | 80061 | 1538 | 0 | 2496 | 754 | 4498 | 82519 | 36 | 1849 | 0 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 40107 | 80002 | 80000 | 80100 | 40153 | 40110 | 40094 | 40146 | 40108 |
| 80204 | 40190 | 301 | 1 | 0 | 0 | 1 | 0 | 0 | 9927 | 41 | 2289 | 1 | 0 | 0 | 1472 | 5 | 196 | 40144 | 2272 | 404 | 352 | 25 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1843792 | 1 | 2 | 40112 | 40193 | 40170 | 30067 | 3 | 30071 | 160100 | 200 | 80000 | 200 | 160000 | 40150 | 40092 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82472 | 2 | 1397 | 2455 | 7 | 2464 | 80035 | 1494 | 0 | 2480 | 766 | 4634 | 82510 | 19 | 1479 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40144 | 80002 | 80000 | 80100 | 40135 | 40166 | 40154 | 40166 | 40113 |
| 80204 | 40096 | 300 | 1 | 0 | 0 | 1 | 0 | 0 | 10128 | 25 | 2315 | 1 | 0 | 0 | 1472 | 5 | 184 | 40089 | 2261 | 508 | 575 | 36 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844584 | 1 | 2 | 40135 | 40144 | 40146 | 30026 | 3 | 30094 | 160100 | 200 | 80000 | 200 | 160000 | 40119 | 40124 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82489 | 2 | 1767 | 2457 | 8 | 2470 | 80024 | 1503 | 1 | 2480 | 766 | 4567 | 82510 | 34 | 1612 | 0 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 40115 | 80002 | 80000 | 80100 | 40127 | 40140 | 40148 | 40143 | 40102 |
| 80204 | 40148 | 301 | 1 | 0 | 0 | 0 | 0 | 0 | 10002 | 40 | 2319 | 1 | 0 | 0 | 1480 | 3 | 232 | 40143 | 2299 | 221 | 598 | 24 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1844032 | 1 | 2 | 40093 | 40175 | 40126 | 30115 | 3 | 30095 | 160100 | 200 | 80000 | 200 | 160000 | 40133 | 40151 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82469 | 4 | 1650 | 2451 | 8 | 2477 | 80040 | 1512 | 0 | 2480 | 766 | 4546 | 82515 | 41 | 1446 | 0 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 40171 | 80002 | 80000 | 80100 | 40130 | 40157 | 40139 | 40139 | 40165 |
| 80204 | 40137 | 301 | 1 | 1 | 0 | 1 | 0 | 0 | 10011 | 51 | 2288 | 1 | 0 | 0 | 1472 | 4 | 196 | 40122 | 2275 | 500 | 459 | 57 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1845136 | 1 | 2 | 40097 | 40126 | 40162 | 30029 | 3 | 30090 | 160100 | 200 | 80000 | 200 | 160000 | 40140 | 40113 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82480 | 8 | 1689 | 2431 | 13 | 2472 | 80030 | 1519 | 0 | 2484 | 762 | 4613 | 82506 | 20 | 1654 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40166 | 80002 | 80000 | 80100 | 40133 | 40118 | 40131 | 40146 | 40128 |
| 80204 | 40116 | 300 | 1 | 0 | 0 | 0 | 0 | 0 | 9831 | 33 | 2298 | 1 | 0 | 0 | 1464 | 6 | 248 | 40145 | 2270 | 423 | 464 | 49 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1843768 | 1 | 2 | 40107 | 40160 | 40187 | 30040 | 3 | 30055 | 160100 | 200 | 80000 | 200 | 160000 | 40116 | 40156 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82464 | 2 | 1435 | 2427 | 6 | 2495 | 80036 | 1521 | 1 | 2476 | 766 | 4555 | 82506 | 24 | 1162 | 0 | 2 | 0 | 5110 | 1 | 16 | 1 | 1 | 40100 | 80002 | 80000 | 80100 | 40149 | 40150 | 40124 | 40153 | 40113 |
| 80204 | 40133 | 300 | 1 | 0 | 0 | 0 | 0 | 0 | 10002 | 58 | 2302 | 1 | 0 | 0 | 1520 | 8 | 228 | 40139 | 2254 | 580 | 537 | 91 | 25 | 160102 | 80102 | 80000 | 80100 | 80000 | 400535 | 1843120 | 1 | 2 | 40132 | 40123 | 40200 | 30073 | 3 | 30115 | 160100 | 200 | 80000 | 200 | 160000 | 40117 | 40146 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 82488 | 3 | 1615 | 2416 | 2 | 2464 | 80045 | 1536 | 0 | 2496 | 756 | 4594 | 82499 | 31 | 1442 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 40122 | 80002 | 80000 | 80100 | 40187 | 40115 | 40163 | 40128 | 40162 |
Result (median cycles for code divided by count): 0.5017
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 61 | 67 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80034 | 40196 | 300 | 3 | 3 | 3 | 0 | 0 | 10305 | 58 | 2333 | 1 | 1248 | 12 | 264 | 40128 | 2260 | 675 | 523 | 77 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1846076 | 1 | 0 | 2 | 40101 | 40138 | 40132 | 30094 | 3 | 30118 | 160010 | 20 | 80000 | 20 | 160000 | 40143 | 40121 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82504 | 26 | 1456 | 2436 | 10 | 2478 | 80054 | 1543 | 0 | 2501 | 986 | 4744 | 82509 | 47 | 1828 | 14 | 0 | 0 | 5020 | 0 | 0 | 5 | 16 | 4 | 2 | 40115 | 80002 | 80000 | 80010 | 40124 | 40116 | 40107 | 40133 | 40159 |
| 80024 | 40135 | 300 | 3 | 3 | 0 | 0 | 0 | 10275 | 61 | 2344 | 1 | 1464 | 10 | 268 | 40144 | 2314 | 597 | 649 | 24 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1843292 | 1 | 0 | 2 | 40118 | 40293 | 40289 | 30049 | 3 | 30089 | 160010 | 20 | 80000 | 20 | 160000 | 40123 | 40159 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82504 | 18 | 919 | 2460 | 8 | 2491 | 80046 | 1538 | 0 | 2490 | 754 | 4676 | 82521 | 53 | 1067 | 14 | 0 | 0 | 5020 | 0 | 0 | 3 | 17 | 5 | 2 | 40128 | 80002 | 80000 | 80010 | 40113 | 40140 | 40128 | 40149 | 40129 |
| 80024 | 40150 | 300 | 2 | 0 | 2 | 0 | 0 | 10116 | 81 | 2278 | 1 | 1472 | 2 | 776 | 40102 | 2313 | 412 | 451 | 24 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1843124 | 1 | 0 | 2 | 40076 | 40116 | 40110 | 30057 | 3 | 30099 | 160010 | 20 | 80000 | 20 | 160000 | 40112 | 40156 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82499 | 14 | 1625 | 2476 | 1 | 2495 | 80039 | 1514 | 0 | 2496 | 748 | 4594 | 82522 | 47 | 754 | 14 | 0 | 0 | 5020 | 0 | 0 | 4 | 16 | 4 | 4 | 40129 | 80002 | 80000 | 80010 | 40090 | 40135 | 40130 | 40136 | 40100 |
| 80024 | 40148 | 301 | 1 | 0 | 1 | 0 | 0 | 10074 | 50 | 2345 | 1 | 1512 | 4 | 196 | 40076 | 2305 | 251 | 392 | 21 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1842404 | 1 | 0 | 2 | 40083 | 40093 | 40145 | 30043 | 3 | 30062 | 160010 | 20 | 80000 | 20 | 160000 | 40123 | 40102 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82510 | 16 | 1384 | 2472 | 11 | 2475 | 80033 | 1484 | 0 | 2504 | 254 | 4600 | 82510 | 52 | 1110 | 14 | 0 | 0 | 5020 | 0 | 0 | 4 | 17 | 4 | 2 | 40198 | 80002 | 80000 | 80010 | 40167 | 40142 | 40102 | 40122 | 40101 |
| 80024 | 40132 | 301 | 1 | 0 | 0 | 0 | 0 | 10212 | 44 | 2316 | 1 | 1272 | 4 | 236 | 40072 | 2290 | 325 | 202 | 34 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1842141 | 1 | 0 | 2 | 40095 | 40118 | 40137 | 30027 | 3 | 30080 | 160010 | 20 | 80000 | 20 | 160000 | 40127 | 40112 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82506 | 14 | 865 | 2470 | 10 | 2502 | 80036 | 1523 | 0 | 2492 | 1000 | 4583 | 82533 | 33 | 987 | 14 | 0 | 0 | 5020 | 0 | 0 | 4 | 17 | 4 | 3 | 40104 | 80002 | 80000 | 80010 | 40089 | 40156 | 40106 | 40150 | 40134 |
| 80024 | 40143 | 300 | 2 | 2 | 1 | 0 | 0 | 10149 | 58 | 2341 | 1 | 1008 | 5 | 204 | 40088 | 2316 | 405 | 449 | 31 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1840989 | 1 | 0 | 2 | 40079 | 40153 | 40091 | 30044 | 3 | 30089 | 160010 | 20 | 80000 | 20 | 160000 | 40123 | 40111 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82520 | 15 | 1498 | 2487 | 5 | 2506 | 80049 | 1540 | 2 | 2500 | 254 | 4660 | 82499 | 35 | 1371 | 14 | 2 | 0 | 5020 | 0 | 0 | 2 | 17 | 2 | 4 | 40146 | 80002 | 80000 | 80010 | 40144 | 40127 | 40113 | 40160 | 40153 |
| 80024 | 40151 | 300 | 1 | 0 | 0 | 0 | 0 | 10149 | 51 | 2339 | 1 | 1728 | 4 | 200 | 40109 | 2298 | 640 | 234 | 17 | 25 | 160012 | 80012 | 80000 | 80010 | 80119 | 400083 | 1844204 | 0 | 0 | 2 | 40234 | 40105 | 40074 | 30030 | 3 | 30129 | 160010 | 20 | 80000 | 20 | 160000 | 40098 | 40118 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82516 | 14 | 459 | 2476 | 12 | 2500 | 80042 | 1496 | 1 | 2504 | 1138 | 4693 | 82526 | 31 | 814 | 14 | 0 | 0 | 5020 | 0 | 0 | 4 | 17 | 4 | 2 | 40102 | 80002 | 80000 | 80010 | 40106 | 40129 | 40121 | 40103 | 40110 |
| 80024 | 40103 | 301 | 2 | 0 | 0 | 0 | 0 | 10161 | 58 | 2310 | 1 | 1448 | 6 | 728 | 40126 | 2248 | 566 | 444 | 36 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1844324 | 1 | 0 | 2 | 40118 | 40118 | 40111 | 30096 | 3 | 30083 | 160010 | 20 | 80000 | 20 | 160000 | 40127 | 40118 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82510 | 15 | 883 | 2468 | 15 | 2495 | 80036 | 1531 | 0 | 2501 | 772 | 4668 | 82510 | 34 | 1261 | 14 | 0 | 0 | 5020 | 10 | 3 | 2 | 17 | 2 | 4 | 40135 | 80002 | 80000 | 80010 | 40137 | 40150 | 40118 | 40145 | 40105 |
| 80024 | 40121 | 301 | 1 | 1 | 1 | 0 | 0 | 9966 | 49 | 2343 | 1 | 1496 | 4 | 224 | 40082 | 2273 | 347 | 842 | 46 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1842886 | 1 | 10 | 2 | 40133 | 40139 | 40109 | 30033 | 3 | 30142 | 160010 | 20 | 80000 | 20 | 160000 | 40085 | 40127 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82507 | 14 | 1126 | 2431 | 11 | 2493 | 80031 | 1556 | 0 | 2488 | 254 | 4526 | 82502 | 30 | 1113 | 14 | 0 | 1 | 5020 | 10 | 6 | 2 | 17 | 2 | 4 | 40174 | 80002 | 80000 | 80010 | 40156 | 40104 | 40094 | 40094 | 40105 |
| 80024 | 40431 | 300 | 1 | 0 | 1 | 0 | 0 | 10185 | 54 | 2310 | 1 | 1448 | 5 | 292 | 40086 | 2274 | 394 | 189 | 18 | 25 | 160012 | 80012 | 80000 | 80010 | 80000 | 400083 | 1844252 | 0 | 10 | 2 | 40112 | 40141 | 40128 | 30081 | 3 | 30127 | 160010 | 20 | 80000 | 20 | 160000 | 40121 | 40128 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 82508 | 15 | 720 | 2434 | 10 | 2490 | 80044 | 1548 | 0 | 2496 | 254 | 4679 | 82499 | 42 | 1555 | 14 | 0 | 0 | 5020 | 10 | 9 | 4 | 17 | 4 | 4 | 40159 | 80002 | 80000 | 80010 | 40138 | 40157 | 40107 | 40131 | 40131 |