Firestorm: STR (register, D) measurements

Code:

  str d0, [x6, x7]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	554	4	0	0	1	527	16	16	1	25	1000	1000	1000	22352	0	515	540	542	355	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	42	0	1002	0	6	1002	2	0	73	2	16	1	1	540	1000	541	541	544	544	544
1004	543	4	0	3	1	527	16	16	0	25	1000	1000	1000	22448	1	527	542	542	355	3	398	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	0	42	73	1	16	1	1	539	1000	541	544	543	543	543
1004	542	4	0	3	0	527	16	16	1	25	1000	1000	1000	23024	0	517	542	540	355	3	401	1000	1000	3000	540	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1000	0	0	73	1	16	1	1	540	1000	543	543	543	541	544
1004	540	4	0	0	0	528	16	16	6	25	1000	1000	1000	22448	0	517	542	540	356	3	400	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	0	0	1000	0	0	1000	0	42	73	1	16	1	1	539	1000	543	543	543	541	543
1004	540	4	0	3	1	527	16	16	1	25	1000	1000	1000	22352	0	517	540	543	355	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	0	0	1002	0	2	1002	2	0	73	1	16	1	1	539	1000	541	543	543	555	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22352	0	515	540	543	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	1	1002	0	2	1002	2	0	73	1	16	1	1	540	1000	544	544	544	544	544
1004	543	4	0	3	0	527	0	0	0	25	1000	1000	1000	22352	0	515	540	543	355	3	398	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	0	0	1002	0	2	1000	2	0	73	1	16	1	1	539	1000	543	543	541	543	541
1004	540	4	0	3	1	528	0	16	1	25	1000	1000	1000	22472	0	521	543	542	355	3	400	1000	1000	3000	554	542	1	1	1001	1000	1000	1000	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	541	544	543	543	637
1004	542	4	6	3	0	528	16	16	0	25	1000	1000	1000	22472	0	517	542	543	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	1	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	541	543
1004	542	4	0	3	1	528	16	16	0	25	1000	1000	1000	22352	1	518	540	542	353	3	398	1000	1000	3000	540	543	1	1	1001	1000	1000	1000	0	0	1000	0	2	1002	0	42	73	1	16	1	1	539	1000	543	543	543	543	543

Count: 8

Code:

  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40055	300	1	1	1	0	0	0	0	17	1	0	0	1	40039	16	16	0	25	80100	100	80000	100	80007	500	1839959	0	40029	40054	40063	29982	7	30004	80107	200	80016	200	240048	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80016	14	0	0	0	80016	0	1	18	80002	16	0	14	0	1	1	1	5118	0	16	0	0	40049	0	80000	100	40053	40055	40048	40048	40064
80204	40054	300	1	1	0	1	0	0	0	20	1	0	0	1	40039	16	16	5	25	80100	100	80000	100	80006	500	1840054	1	40029	40063	40052	29966	7	30006	80106	200	80016	200	240048	40048	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	0	0	80014	0	0	14	80002	16	44	14	0	1	1	1	5118	0	16	0	0	40051	0	80000	100	40055	40053	40055	40054	40055
80204	40052	300	1	1	0	1	0	0	9	17	0	0	0	1	40039	16	16	1	25	80100	100	80000	100	80006	500	1840035	0	40029	40047	40054	29966	7	30006	80106	200	80016	200	240048	40052	40051	1	1	80201	100	99	100	100	80000	80000	100	80015	14	44	1	0	80014	0	0	19	80002	16	44	14	0	1	1	1	5118	0	16	0	0	40051	0	80000	100	40048	40048	40055	40053	40055
80204	40052	300	1	1	1	0	0	0	0	19	1	0	0	1	40039	16	16	1	25	80100	100	80000	100	80007	500	1839718	1	40029	40052	40047	29966	7	30006	80106	200	80016	200	240048	40053	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	44	0	0	80016	0	0	18	80002	16	44	14	1	1	1	1	5118	0	16	0	0	40049	0	80000	100	40055	40055	40048	40055	40055
80204	40053	300	1	1	1	0	0	0	0	17	1	0	0	1	40032	16	15	1	25	80100	100	80000	100	80006	500	1840054	1	40027	40054	40054	29973	7	30015	80106	200	80016	200	240048	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80016	15	44	0	1	80016	0	1	16	80000	16	44	14	3	1	1	1	5317	3	88	3	2	41941	1	80000	100	42313	41852	42175	42270	42263
80204	41215	316	1	0	0	0	9	16	2112	1425	0	0	0	1	42260	16	16	1254	505	80764	102	81020	105	81629	511	1923615	0	41744	41716	42000	30710	124	31494	80221	200	80143	200	240048	40054	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	1	0	80016	0	0	17	80002	16	44	14	1	1	1	1	5118	0	16	0	0	40044	0	80000	100	40055	40053	40048	40054	40048
80204	40051	299	1	1	1	0	0	0	3	19	1	0	0	1	40032	0	16	5	25	80100	100	80000	100	80121	500	1839960	0	40038	41296	40607	30528	97	30928	81195	208	80381	200	243333	41566	40468	11	1	80201	100	99	100	100	80000	80000	100	80015	15	44	0	1	80076	0	2	18	80000	16	46	14	1	1	1	1	5136	1	96	2	2	41129	1	80000	100	41901	41025	41442	40611	40052
80204	40054	300	1	1	1	1	0	0	21	20	1	0	0	1	40737	16	16	583	415	80762	100	80300	100	80007	500	1840054	0	40027	40192	41848	30154	7	30003	80106	200	80016	200	240048	41158	40881	4	1	80201	100	99	100	100	80000	80000	100	80734	14	44	236	0	80556	0	6	6462	80002	16	44	14	1	1	1	1	5118	0	16	1	0	40876	1	80000	100	41305	41017	40887	41305	41443
80204	40051	321	1	0	0	0	1	0	0	15	1	0	0	1	41575	16	16	809	325	80700	103	80000	100	80012	500	1839992	0	40023	41853	40054	29964	10	29987	80112	200	80022	200	240066	40047	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	0	2	80016	0	1	18	80002	14	0	14	0	2	1	2	5128	1	23	1	1	40051	0	80000	100	40055	40064	40055	40064	40048
80204	40047	300	1	1	1	1	0	0	0	19	1	0	0	1	40037	16	16	2	25	80100	100	80000	100	80012	500	1839656	0	40029	40054	40052	29958	10	29993	80113	200	80022	200	240066	40054	40052	1	1	80201	100	99	100	100	80000	80000	100	80015	15	44	0	1	80016	0	0	16	80002	16	0	14	1	2	2	2	5128	1	23	1	1	40049	0	80000	100	40064	40048	40053	40055	40055

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	1	0	0	54	3	1	0	0	40028	16	16	1	25	80010	10	80000	10	80000	50	1839352	0	40017	0	40042	40042	29977	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	2	80002	2	0	0	0	0	5020	26	16	25	26	40039	80000	10	40043	40043	40043	40043	40043
80024	40054	300	0	0	0	6	0	1	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40018	0	40040	40040	29977	3	30023	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	2	80002	0	42	0	0	0	5020	16	16	27	14	40039	80000	10	40043	40043	40044	40043	40041
80024	40043	300	0	0	0	6	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	0	40042	40043	29980	3	30020	80010	20	80000	20	240000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	0	80002	0	0	0	0	0	5020	28	16	27	27	40039	80000	10	40043	40124	40041	40044	40043
80024	40043	308	0	0	0	33	3	0	0	0	40025	0	0	0	25	80010	10	80000	10	80000	50	1839448	0	40017	0	40042	40043	29977	3	30020	80010	20	80000	20	240000	40040	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	0	80012	2	0	0	0	0	5020	24	16	16	27	40039	80000	10	40043	40041	40043	40043	40043
80024	40054	300	0	1	1	57	3	1	0	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	40015	0	40040	40044	29978	3	30020	80010	20	80000	20	240000	40054	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	2	80002	2	42	0	0	0	5020	25	16	24	25	40039	80000	10	40043	40043	40043	40043	40043
80024	40043	300	0	0	0	0	3	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	40015	0	40042	40048	29977	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	2	80002	2	0	0	0	0	5020	26	16	20	26	40039	80000	10	40043	40043	40041	40044	40044
80024	40042	300	0	0	0	39	3	1	0	0	40028	16	16	0	25	80010	10	80000	10	80000	50	1839472	0	40018	0	40043	40044	29989	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	2	2	80002	0	42	0	0	0	5020	28	16	27	27	40039	80000	10	40044	40044	40043	40041	40043
80024	40043	300	0	0	0	0	3	0	0	0	40027	0	16	0	40	80010	10	80000	10	80000	50	1839352	1	40015	0	40042	40040	29981	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80000	0	0	80002	0	42	0	0	0	5020	27	16	22	28	40039	80000	10	40043	40044	40041	40043	40043
80024	40042	300	0	0	0	6	3	1	0	2	40027	0	16	0	25	80010	10	80000	10	80000	50	1839448	1	40017	0	40040	40042	29975	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	5	80002	2	42	0	0	0	5020	27	16	25	28	40039	80000	10	40043	40044	40043	40041	40043
80024	40040	300	0	0	0	0	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40018	0	40042	40043	29978	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80000	0	2	80002	2	42	0	0	0	5020	27	16	29	27	40039	80000	10	40044	40041	40043	40043	40043

STR (register, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations