Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STR (register, D)

Test 1: uops

Code:

  str d0, [x6, x7]
  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)031e1f223f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a2a4a7a8acafbcdcache store miss (c0)cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
100555440015271616125100010001000223520515540542355340010001000300054254011100110001000100042010020610022073216115401000541541544544544
1004543403152716160251000100010002244815275425423553398100010003000542542111001100010001000420100202100204273116115391000541544543543543
100454240305271616125100010001000230240517542540355340110001000300054054311100110001000100042010020210000073116115401000543543543541544
100454040005281616625100010001000224480517542540356340010001000300054054011100110001000100000100000100004273116115391000543543543541543
10045404031527161612510001000100022352051754054335534001000100030005405421110011000100010000010020210022073116115391000541543543555543
100454240315271616025100010001000223520515540543355340010001000300054254211100110001000100042110020210022073116115401000544544544544544
100454340305270002510001000100022352051554054335533981000100030005405421110011000100010000010020210002073116115391000543543541543541
10045404031528016125100010001000224720521543542355340010001000300055454211100110001000100000100202100224273116115391000541544543543637
1004542463052816160251000100010002247205175425433553400100010003000542542111001100010001000420100212100224273116115391000543543543541543
100454240315281616025100010001000223521518540542353339810001000300054054311100110001000100000100002100204273116115391000543543543543543

Test 2: throughput

Count: 8

Code:

  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  str d0, [x6, x7]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire (01)cycle (02)030508090b18191e1f2223243a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
802054005530011100001710014003916160258010010080000100800075001839959040029400544006329982730004801072008001620024004840054400541180201100991001008000080000100800161400080016011880002160140111511801600400490800001004005340055400484004840064
8020440054300110100020100140039161652580100100800001008000650018400541400294006340052299667300068010620080016200240048400484005211802011009910010080000800001008001415000800140014800021644140111511801600400510800001004005540053400554005440055
80204400523001101009170001400391616125801001008000010080006500184003504002940047400542996673000680106200800162002400484005240051118020110099100100800008000010080015144410800140019800021644140111511801600400510800001004004840048400554005340055
80204400523001110000191001400391616125801001008000010080007500183971814002940052400472996673000680106200800162002400484005340054118020110099100100800008000010080014154400800160018800021644141111511801600400490800001004005540055400484005540055
80204400533001110000171001400321615125801001008000010080006500184005414002740054400542997373001580106200800162002400484005440054118020110099100100800008000010080016154401800160116800001644143111531738832419411800001004231341852421754227042263
8020441215316100091621121425000142260161612545058076410281020105816295111923615041744417164200030710124314948022120080143200240048400544004711802011009910010080000800001008001414010800160017800021644141111511801600400440800001004005540053400484005440048
802044005129911100031910014003201652580100100800001008012150018399600400384129640607305289730928811952088038120024333341566404681118020110099100100800008000010080015154401800760218800001646141111513619622411291800001004190141025414424061140052
8020440054300111100212010014073716165834158076210080300100800075001840054040027401924184830154730003801062008001620024004841158408814180201100991001008000080000100807341444236080556066462800021644141111511801610408761800001004130541017408874130541443
8020440051321100010015100141575161680932580700103800001008001250018399920400234185340054299641029987801122008002220024006640047400541180201100991001008000080000100800141400280016011880002140140212512812311400510800001004005540064400554006440048
80204400473001111000191001400371616225801001008000010080012500183965604002940054400522995810299938011320080022200240066400544005211802011009910010080000800001008001515440180016001680002160141222512812311400490800001004006440048400534005540055

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030418191e1f22243a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a2a4a7a8acafbcdcache store miss (c0)c2c3cdcfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
8002540042300100543100400281616125800101080000108000050183935204001704004240042299773300208001020800002024000040042400401180021109101080000800001080000420800020280002200005020261625264003980000104004340043400434004340043
8002440054300000601004002516160258001010800001080000501839352140018040040400402997733002380010208000020240000400434004311800211091010800008000010800004208000202800020420005020161627144003980000104004340043400444004340041
80024400433000006300040027161602580010108000010800005018394480400170400424004329980330020800102080000202400004004240043118002110910108000080000108000000800020080002000005020281627274003980000104004340124400414004440043
80024400433080003330004002500025800101080000108000050183944804001704004240043299773300208001020800002024000040040400431180021109101080000800001080000420800020080012200005020241616274003980000104004340041400434004340043
8002440054300011573100400271616125800101080000108000050183944814001504004040044299783300208001020800002024000040054400421180021109101080000800001080000008000202800022420005020251624254003980000104004340043400434004340043
800244004330000003000400251616025800101080000108000050183944814001504004240048299773300228001020800002024000040040400421180021109101080000800001080000420800020280002200005020261620264003980000104004340043400414004440044
80024400423000003931004002816160258001010800001080000501839472040018040043400442998933002280010208000020240000400404004211800211091010800008000010800004208000222800020420005020281627274003980000104004440044400434004140043
800244004330000003000400270160408001010800001080000501839352140015040042400402998133002280010208000020240000400424004211800211091010800008000010800004208000000800020420005020271622284003980000104004340044400414004340043
800244004230000063102400270160258001010800001080000501839448140017040040400422997533002080010208000020240000400424004011800211091010800008000010800004208000205800022420005020271625284003980000104004340044400434004140043
8002440040300000000004002516160258001010800001080000501839448040018040042400432997833002080010208000020240000400424004211800211091010800008000010800004208000002800022420005020271629274003980000104004440041400434004340043