Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
str q0, [x6, x7]
mov x0, 0 mov x7, 8
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 22 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd store (99) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
1005 | 550 | 4 | 1 | 1 | 1 | 0 | 0 | 21 | 1 | 1 | 537 | 16 | 14 | 5 | 25 | 1000 | 1000 | 1000 | 22956 | 542 | 558 | 550 | 372 | 3 | 416 | 1000 | 1000 | 3000 | 552 | 557 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 15 | 36 | 0 | 1 | 1016 | 0 | 18 | 1002 | 16 | 36 | 14 | 2 | 73 | 3 | 16 | 2 | 2 | 549 | 1000 | 560 | 553 | 553 | 552 | 551 |
1004 | 560 | 4 | 1 | 0 | 1 | 1 | 0 | 17 | 0 | 1 | 545 | 16 | 16 | 5 | 25 | 1000 | 1000 | 1000 | 22956 | 533 | 558 | 550 | 372 | 3 | 418 | 1000 | 1000 | 3000 | 559 | 551 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 14 | 36 | 0 | 1 | 1016 | 0 | 17 | 1002 | 16 | 36 | 14 | 1 | 73 | 2 | 16 | 2 | 2 | 548 | 1000 | 553 | 554 | 553 | 551 | 561 |
1004 | 561 | 4 | 1 | 1 | 0 | 1 | 0 | 20 | 0 | 1 | 543 | 16 | 16 | 1 | 25 | 1000 | 1000 | 1000 | 22836 | 534 | 552 | 559 | 365 | 3 | 417 | 1000 | 1000 | 3000 | 553 | 558 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 16 | 35 | 0 | 1 | 1016 | 0 | 614 | 1002 | 16 | 36 | 14 | 2 | 73 | 2 | 16 | 2 | 2 | 555 | 1000 | 551 | 561 | 560 | 559 | 559 |
1004 | 558 | 4 | 1 | 0 | 1 | 0 | 0 | 18 | 0 | 1 | 535 | 16 | 16 | 5 | 25 | 1000 | 1000 | 1000 | 22908 | 533 | 558 | 551 | 372 | 3 | 408 | 1000 | 1000 | 3000 | 559 | 551 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 16 | 36 | 0 | 1 | 1016 | 0 | 17 | 1002 | 16 | 36 | 14 | 2 | 73 | 2 | 16 | 2 | 2 | 550 | 1000 | 559 | 553 | 554 | 553 | 552 |
1004 | 550 | 4 | 1 | 0 | 0 | 1 | 0 | 19 | 0 | 1 | 544 | 16 | 16 | 5 | 25 | 1000 | 1000 | 1000 | 23340 | 527 | 551 | 559 | 365 | 3 | 416 | 1000 | 1000 | 3000 | 552 | 557 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 14 | 36 | 0 | 0 | 1016 | 0 | 17 | 1002 | 16 | 34 | 14 | 1 | 73 | 2 | 16 | 2 | 2 | 550 | 1000 | 554 | 553 | 551 | 562 | 559 |
1004 | 557 | 4 | 1 | 1 | 1 | 1 | 0 | 18 | 0 | 1 | 537 | 16 | 14 | 5 | 25 | 1000 | 1000 | 1000 | 23220 | 524 | 558 | 553 | 374 | 3 | 410 | 1000 | 1000 | 3000 | 561 | 559 | 1 | 1 | 1001 | 1000 | 1000 | 1016 | 14 | 36 | 2 | 0 | 1016 | 0 | 18 | 1002 | 16 | 36 | 14 | 1 | 73 | 2 | 16 | 2 | 2 | 555 | 1000 | 559 | 559 | 559 | 559 | 554 |
1004 | 552 | 4 | 1 | 0 | 1 | 0 | 0 | 20 | 0 | 1 | 546 | 16 | 16 | 2 | 25 | 1000 | 1000 | 1000 | 22932 | 533 | 552 | 561 | 372 | 3 | 416 | 1000 | 1000 | 3000 | 559 | 549 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 16 | 36 | 0 | 1 | 1016 | 0 | 20 | 1002 | 16 | 36 | 14 | 0 | 73 | 2 | 16 | 2 | 2 | 549 | 1000 | 559 | 559 | 553 | 553 | 553 |
1004 | 551 | 4 | 1 | 1 | 1 | 1 | 0 | 19 | 0 | 1 | 543 | 16 | 16 | 6 | 25 | 1000 | 1000 | 1000 | 23221 | 527 | 550 | 558 | 365 | 3 | 417 | 1000 | 1000 | 3000 | 552 | 559 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 14 | 36 | 0 | 0 | 1016 | 1 | 18 | 1000 | 16 | 36 | 14 | 0 | 73 | 2 | 16 | 2 | 2 | 547 | 1000 | 560 | 553 | 552 | 550 | 561 |
1004 | 558 | 4 | 1 | 0 | 1 | 1 | 0 | 21 | 0 | 1 | 546 | 16 | 16 | 0 | 25 | 1000 | 1000 | 1000 | 23220 | 525 | 557 | 553 | 374 | 3 | 410 | 1000 | 1000 | 3000 | 561 | 559 | 1 | 1 | 1001 | 1000 | 1000 | 1015 | 14 | 36 | 4 | 2 | 1016 | 0 | 19 | 1002 | 16 | 36 | 14 | 0 | 73 | 2 | 16 | 2 | 2 | 555 | 1000 | 560 | 559 | 559 | 553 | 553 |
1004 | 553 | 4 | 1 | 1 | 1 | 0 | 0 | 17 | 0 | 1 | 544 | 16 | 16 | 7 | 25 | 1000 | 1000 | 1000 | 23246 | 528 | 550 | 559 | 364 | 3 | 416 | 1000 | 1000 | 3000 | 551 | 558 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 15 | 36 | 0 | 0 | 1016 | 0 | 17 | 1002 | 16 | 34 | 14 | 2 | 73 | 2 | 16 | 2 | 2 | 550 | 1000 | 559 | 559 | 553 | 554 | 553 |
Count: 8
Code:
str q0, [x6, x7] str q0, [x6, x7] str q0, [x6, x7] str q0, [x6, x7] str q0, [x6, x7] str q0, [x6, x7] str q0, [x6, x7] str q0, [x6, x7]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1f | 22 | 3a | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80205 | 40052 | 300 | 1 | 1 | 1 | 19 | 1 | 1 | 40037 | 16 | 0 | 10 | 25 | 80100 | 100 | 80000 | 100 | 80007 | 500 | 1839939 | 0 | 40033 | 40052 | 40059 | 29971 | 7 | 30011 | 80106 | 200 | 80144 | 200 | 240048 | 40052 | 40052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 36 | 4 | 0 | 80016 | 26 | 0 | 16 | 80002 | 14 | 36 | 14 | 2 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40049 | 0 | 80000 | 100 | 40048 | 40059 | 40050 | 40060 | 40060 |
80204 | 40047 | 300 | 1 | 1 | 1 | 20 | 1 | 1 | 40032 | 0 | 16 | 11 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1840246 | 1 | 40033 | 40058 | 40050 | 29979 | 7 | 30004 | 80106 | 200 | 80016 | 200 | 240048 | 40060 | 40051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 16 | 36 | 1 | 0 | 80016 | 34 | 0 | 20 | 80002 | 16 | 36 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 1 | 40047 | 0 | 80000 | 100 | 40059 | 40048 | 40048 | 40059 | 40059 |
80204 | 40052 | 300 | 1 | 1 | 1 | 20 | 0 | 1 | 40038 | 16 | 16 | 1 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839718 | 1 | 40022 | 40052 | 40059 | 29977 | 7 | 29999 | 80107 | 200 | 80016 | 200 | 240048 | 40059 | 40059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 14 | 0 | 1 | 0 | 80014 | 19 | 0 | 92 | 80120 | 16 | 36 | 14 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40049 | 0 | 80000 | 100 | 40048 | 40060 | 40053 | 40048 | 40062 |
80204 | 40047 | 300 | 1 | 0 | 1 | 14 | 0 | 1 | 40043 | 16 | 16 | 9 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839718 | 1 | 40025 | 40059 | 40059 | 29977 | 7 | 30013 | 80106 | 200 | 80016 | 200 | 240048 | 40059 | 40059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 15 | 36 | 0 | 0 | 80016 | 2 | 0 | 14 | 80002 | 16 | 36 | 14 | 2 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40054 | 0 | 80000 | 100 | 40059 | 40052 | 40060 | 40048 | 40054 |
80204 | 40047 | 300 | 1 | 0 | 0 | 14 | 0 | 1 | 40032 | 16 | 16 | 4 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1840200 | 1 | 40034 | 40051 | 40047 | 29966 | 7 | 30010 | 80106 | 200 | 80016 | 200 | 240048 | 40047 | 40052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 0 | 0 | 0 | 80016 | 64 | 0 | 14 | 80002 | 16 | 36 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40044 | 0 | 80000 | 100 | 40060 | 40048 | 40059 | 40052 | 40053 |
80204 | 40058 | 299 | 1 | 1 | 0 | 14 | 1 | 1 | 40032 | 16 | 16 | 7 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839718 | 1 | 40034 | 40060 | 40052 | 29970 | 7 | 30010 | 80107 | 200 | 80016 | 200 | 240048 | 40050 | 40047 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 15 | 36 | 0 | 0 | 80014 | 10 | 1 | 14 | 80002 | 16 | 0 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40044 | 0 | 80000 | 100 | 40058 | 40048 | 40059 | 40048 | 40061 |
80204 | 40047 | 300 | 1 | 0 | 0 | 21 | 0 | 1 | 40037 | 14 | 0 | 6 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839718 | 1 | 40027 | 40059 | 40059 | 29967 | 7 | 29999 | 80106 | 200 | 80016 | 200 | 240048 | 40059 | 40061 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 15 | 35 | 0 | 0 | 80016 | 9 | 1 | 25 | 80002 | 16 | 36 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40049 | 0 | 80000 | 100 | 40053 | 40059 | 40048 | 40058 | 40062 |
80204 | 40058 | 300 | 1 | 0 | 0 | 19 | 0 | 1 | 40035 | 16 | 16 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839939 | 1 | 40033 | 40052 | 40047 | 29966 | 7 | 30011 | 80106 | 200 | 80016 | 200 | 240048 | 40052 | 40059 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 14 | 36 | 0 | 0 | 80014 | 0 | 1 | 3233 | 80002 | 16 | 0 | 14 | 1 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40055 | 0 | 80000 | 100 | 40048 | 40060 | 40048 | 40048 | 40048 |
80204 | 40051 | 300 | 1 | 0 | 0 | 21 | 0 | 1 | 40032 | 0 | 16 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80006 | 500 | 1839718 | 1 | 40022 | 40052 | 40058 | 29966 | 7 | 30010 | 80107 | 200 | 80016 | 200 | 240048 | 40047 | 40058 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80014 | 15 | 36 | 0 | 0 | 80014 | 24 | 0 | 17 | 80000 | 16 | 0 | 14 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40055 | 0 | 80000 | 100 | 40054 | 40049 | 40048 | 40062 | 40048 |
80204 | 40047 | 300 | 1 | 0 | 0 | 19 | 0 | 1 | 40043 | 16 | 16 | 6 | 25 | 80100 | 100 | 80000 | 100 | 80007 | 500 | 1839718 | 1 | 40034 | 40058 | 40050 | 29966 | 7 | 30005 | 80106 | 200 | 80016 | 200 | 240048 | 40061 | 40051 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 80015 | 15 | 36 | 0 | 0 | 80014 | 1 | 1 | 14 | 80002 | 16 | 36 | 14 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 40057 | 0 | 80000 | 100 | 40059 | 40053 | 40060 | 40053 | 40060 |
Result (median cycles for code divided by count): 0.5005
retire uop (01) | cycle (02) | 03 | 1e | 1f | 22 | 23 | 24 | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd store (99) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80025 | 40045 | 300 | 0 | 3 | 1 | 0 | 0 | 40025 | 16 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839808 | 1 | 40017 | 0 | 40040 | 40050 | 29975 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80002 | 0 | 0 | 203 | 80002 | 0 | 34 | 0 | 5020 | 15 | 16 | 5 | 6 | 40039 | 80000 | 10 | 40043 | 40041 | 40043 | 40050 | 40041 |
80024 | 40053 | 300 | 0 | 6 | 0 | 0 | 0 | 40025 | 16 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 0 | 40017 | 0 | 40040 | 40042 | 29977 | 3 | 30020 | 80010 | 20 | 80000 | 20 | 240000 | 40040 | 40050 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80000 | 0 | 0 | 243 | 80002 | 2 | 0 | 0 | 5020 | 11 | 16 | 5 | 11 | 40037 | 80000 | 10 | 40052 | 40041 | 40041 | 40043 | 40043 |
80024 | 40042 | 299 | 0 | 0 | 1 | 0 | 0 | 40025 | 0 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839856 | 0 | 40025 | 0 | 40042 | 40040 | 29977 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 0 | 224 | 80002 | 2 | 34 | 0 | 5020 | 5 | 16 | 4 | 5 | 40039 | 80000 | 10 | 40043 | 40043 | 40043 | 40051 | 40043 |
80024 | 40052 | 300 | 0 | 3 | 0 | 0 | 0 | 40027 | 16 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839808 | 0 | 40015 | 0 | 40042 | 40040 | 29975 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80000 | 0 | 0 | 170 | 80002 | 2 | 0 | 0 | 5020 | 11 | 16 | 5 | 12 | 40037 | 80000 | 10 | 40052 | 40043 | 40043 | 40041 | 40051 |
80024 | 40043 | 300 | 0 | 3 | 0 | 0 | 0 | 40027 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839808 | 1 | 40017 | 0 | 40051 | 40042 | 29977 | 3 | 30020 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 0 | 245 | 80002 | 0 | 34 | 0 | 5020 | 11 | 16 | 5 | 4 | 40039 | 80000 | 10 | 40043 | 40043 | 40043 | 40051 | 40041 |
80024 | 40040 | 299 | 0 | 0 | 1 | 0 | 0 | 40025 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 0 | 40015 | 0 | 40051 | 40040 | 29977 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 0 | 158 | 80000 | 2 | 34 | 0 | 5020 | 4 | 16 | 10 | 5 | 40039 | 80000 | 10 | 40043 | 40041 | 40043 | 40043 | 40041 |
80024 | 40042 | 299 | 0 | 3 | 0 | 0 | 0 | 40027 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839352 | 1 | 40017 | 0 | 40040 | 40051 | 29975 | 3 | 30020 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 0 | 242 | 80002 | 2 | 0 | 0 | 5020 | 12 | 16 | 10 | 4 | 40039 | 80000 | 10 | 40041 | 40041 | 40043 | 40043 | 40043 |
80024 | 40042 | 300 | 0 | 3 | 0 | 0 | 0 | 40027 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839808 | 0 | 40015 | 0 | 40042 | 40051 | 29986 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40042 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80002 | 0 | 0 | 263 | 80002 | 2 | 34 | 0 | 5020 | 7 | 16 | 4 | 6 | 40039 | 80000 | 10 | 40050 | 40043 | 40043 | 40043 | 40043 |
80024 | 40045 | 300 | 0 | 0 | 0 | 0 | 0 | 40027 | 16 | 16 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 0 | 40017 | 0 | 40042 | 40042 | 29975 | 3 | 30030 | 80010 | 20 | 80000 | 20 | 240000 | 40050 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 34 | 0 | 0 | 80000 | 0 | 0 | 207 | 80002 | 12 | 34 | 0 | 5020 | 4 | 16 | 10 | 6 | 40039 | 80000 | 10 | 40041 | 40043 | 40043 | 40043 | 40043 |
80024 | 40040 | 300 | 0 | 9 | 1 | 0 | 0 | 40025 | 16 | 0 | 2 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1839424 | 1 | 40015 | 0 | 40040 | 40042 | 29977 | 3 | 30022 | 80010 | 20 | 80000 | 20 | 240000 | 40040 | 40042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 10 | 80000 | 0 | 0 | 0 | 0 | 80000 | 0 | 0 | 234 | 80002 | 2 | 34 | 0 | 5020 | 5 | 16 | 5 | 8 | 40047 | 80000 | 10 | 40041 | 40041 | 40041 | 40041 | 40043 |