Firestorm: STR (register, S) measurements

Code:

  str s0, [x6, x7]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	560	4	1	0	1	0	21	1	0	1	537	16	16	6	25	1000	1000	1000	23220	0	525	557	553	374	3	410	1000	1000	3000	549	558	1	1	1001	1000	1000	1015	15	36	0	0	1016	0	1	20	1002	16	36	14	0	73	1	16	1	1	546	1000	553	552	561	559	558
1004	558	4	1	0	0	0	19	1	0	1	538	16	16	5	25	1000	1000	1000	23247	1	534	559	560	371	3	416	1000	1000	3000	559	560	1	1	1001	1000	1000	1014	14	36	0	2	1016	0	1	16	1002	16	36	14	1	73	1	16	1	1	557	1000	559	560	560	560	553
1004	552	4	1	1	0	0	21	0	0	1	544	15	16	2	25	1000	1000	1000	22908	0	534	558	551	372	3	410	1000	1000	3000	558	552	1	1	1001	1000	1000	1015	15	36	1	0	1016	0	0	16	1002	16	36	14	0	73	1	16	1	1	548	1000	553	554	553	551	561
1004	561	4	1	1	0	0	19	1	0	1	535	16	16	5	25	1000	1000	1000	23220	0	525	559	552	373	3	410	1000	1000	3000	558	552	1	1	1001	1000	1000	1014	15	36	1	1	1016	0	2	18	1002	16	36	14	0	73	1	16	1	1	549	1000	560	560	553	553	553
1004	551	4	1	1	0	0	21	1	0	1	538	16	16	5	25	1000	1000	1000	23247	1	534	559	560	371	3	415	1000	1000	3000	559	560	1	1	1001	1000	1000	1016	16	36	0	0	1016	0	1	20	1002	16	36	14	3	73	1	16	1	1	548	1000	559	554	553	551	561
1004	561	4	1	0	1	0	19	1	0	1	534	16	16	5	25	1000	1000	1000	23220	0	524	558	553	374	3	408	1000	1000	3000	558	552	1	1	1001	1000	1000	1014	14	36	0	1	1016	0	0	20	1002	16	36	14	1	73	1	16	1	1	557	1000	553	552	550	559	559
1004	558	4	1	0	1	0	19	1	0	1	542	16	16	3	25	1000	1000	1000	22908	1	526	558	552	373	3	417	1000	1000	3000	559	549	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	1	18	1002	16	36	14	1	73	1	16	1	1	556	1000	561	560	560	560	560
1004	559	4	1	1	0	0	18	1	0	1	543	16	16	3	25	1000	1000	1000	23316	0	527	552	559	365	3	418	1000	1000	3000	558	550	1	1	1001	1000	1000	1015	15	36	0	1	1016	0	0	17	1002	16	36	14	1	73	1	16	1	1	547	1000	553	553	552	561	561
1004	558	4	1	0	1	0	19	1	0	1	536	16	16	5	25	1000	1000	1000	23268	1	534	552	559	365	3	416	1000	1000	3000	552	559	1	1	1001	1000	1000	1014	15	35	0	2	1016	0	1	18	1002	16	36	14	1	73	1	16	1	1	556	1000	558	560	560	555	553
1004	552	4	1	1	1	0	19	1	0	1	546	16	16	2	25	1000	1000	1000	23268	0	536	559	551	371	3	417	1000	1000	3000	560	559	1	1	1001	1000	1000	1015	15	36	0	0	1016	0	0	17	1002	16	34	14	1	73	1	16	1	1	549	1000	560	560	553	552	551

Count: 8

Code:

  str s0, [x6, x7]
  str s0, [x6, x7]
  str s0, [x6, x7]
  str s0, [x6, x7]
  str s0, [x6, x7]
  str s0, [x6, x7]
  str s0, [x6, x7]
  str s0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40052	300	1	1	0	0	0	0	60	19	1	0	1	40035	16	16	7	25	80100	100	80000	100	80007	500	1840246	0	40024	40059	40059	29977	7	30013	80107	200	80016	200	240048	40051	40053	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	0	1	80016	0	0	19	80002	16	36	14	0	1	1	1	5118	2	16	0	0	40055	0	80000	100	40059	40053	40060	40054	40060
80204	40051	300	1	0	0	0	0	0	0	19	1	0	1	40037	16	16	0	25	80100	100	80000	100	80007	500	1840200	0	40028	40058	40058	29976	7	30009	80106	200	80016	200	240048	40052	40059	1	1	80201	100	99	100	100	80000	80000	100	80016	15	36	0	0	80016	0	2	20	80002	16	36	14	0	1	1	1	5118	0	16	0	0	40057	0	80000	100	40049	40053	40059	40053	40060
80204	40050	300	1	1	0	1	0	0	225	283	1	0	1	40037	0	16	5	25	80100	100	80000	100	80007	500	1839719	0	40028	40058	40060	29977	7	30002	80107	200	80016	200	240048	40059	40058	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	0	0	80014	0	1	21	80002	16	36	14	0	1	1	1	5118	0	16	0	0	40049	0	80000	100	40052	40060	40048	40059	40061
80204	40058	300	1	1	0	1	0	0	108	19	1	0	1	40037	16	16	0	25	80100	100	80000	100	80006	500	1840277	0	40028	40058	40058	29978	7	30002	80106	200	80016	200	240048	40047	40059	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	0	2	80016	0	1	20	80002	16	35	14	0	1	1	1	5118	0	16	0	0	40056	0	80000	100	40060	40051	40059	40051	40053
80204	40060	300	1	1	0	1	0	0	108	21	1	0	1	40033	16	0	1	25	80100	100	80000	100	80006	500	1839958	0	40033	40050	40052	29971	7	30004	80106	200	80016	200	240048	40060	40052	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	1	0	80016	0	1	18	80002	14	36	14	1	1	1	1	5118	0	16	0	0	40055	0	80000	100	40061	40060	40061	40059	40058
80204	40052	300	1	1	0	0	0	0	105	20	1	0	1	40117	16	16	6	25	80100	100	80000	100	80006	500	1840247	0	40022	40059	40061	29977	7	30002	80107	200	80016	200	240048	40058	40058	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	0	1	80016	0	1	19	80002	16	36	14	0	1	1	1	5118	0	16	0	0	40058	0	80000	100	40060	40053	40059	40053	40059
80204	40051	300	1	0	1	1	0	0	501	18	1	0	1	40045	16	16	4	25	80100	100	80000	100	80006	500	1840342	0	40027	40057	40060	29979	7	30003	80106	200	80016	200	240048	40058	40060	1	1	80201	100	99	100	100	80000	80000	100	80015	15	34	0	0	80016	0	1	18	80002	16	36	14	0	1	1	1	5118	0	16	0	0	40055	0	80000	100	40054	40060	40053	40062	40052
80204	40059	300	1	0	1	1	0	0	93	17	1	0	1	40038	16	16	1	25	80100	100	80000	100	80007	500	1839958	0	40033	40050	40052	29971	7	30001	80106	200	80016	200	240048	40058	40059	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	0	0	80016	0	2	14	80002	16	36	14	1	1	1	1	5118	0	16	0	0	40058	0	80000	100	40060	40048	40357	40053	40059
80204	40047	300	1	1	1	2	0	0	0	21	1	0	1	40044	16	16	11	25	80100	100	80000	100	80006	500	1840294	0	40027	40058	40058	29978	7	30013	80106	200	80016	200	240048	40059	40059	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	0	0	80016	0	0	19	80002	16	36	14	0	1	1	1	5118	0	16	0	0	40055	0	80000	100	40048	40061	40059	40051	40060
80204	40059	300	1	1	0	0	0	0	477	21	0	0	1	40044	16	16	9	25	80100	100	80000	100	80007	500	1839939	0	40026	40059	40059	30028	7	30002	80107	200	80144	200	240048	40051	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	0	1	80016	0	1	20	80002	16	36	14	1	1	1	1	5118	0	16	0	0	40047	0	80000	100	40060	40052	40059	40053	40059

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	807	3	1	0	0	40028	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	0	40042	40042	29977	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	2	80002	2	42	5021	1	22	16	17	17	40039	80000	10	40043	40041	40044	40043	40044
80024	40042	300	1	894	0	1	0	0	40025	16	16	158	25	80010	10	80000	10	80108	50	1839448	1	40143	0	40323	40318	29977	3	30035	80118	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	0	80002	2	42	5020	0	13	16	8	17	40039	80000	10	40043	40041	40043	40041	40043
80024	40042	299	0	0	3	1	0	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839448	0	40015	0	40043	40043	29977	3	30020	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80000	0	2	80000	0	0	5020	0	16	16	15	17	40040	80000	10	40044	40043	40043	40044	40043
80024	40042	300	0	0	3	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	0	40042	40042	29975	3	30026	80010	20	80000	20	240000	40040	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80000	0	2	80002	2	42	5020	0	17	16	17	17	40037	80000	10	40044	40041	40043	40041	40043
80024	40043	300	0	6	3	1	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	40018	0	40043	40043	29977	3	30026	80010	20	80000	20	240000	40042	40042	1	1	80022	10	9	10	10	80000	80000	10	80000	42	0	80002	0	0	80002	2	42	5020	0	15	16	14	16	40037	80000	10	40043	40043	40043	40055	40043
80024	40042	300	0	0	0	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839472	1	40017	0	40042	40042	29977	3	30024	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	2	80002	2	42	5020	0	17	16	17	17	40276	80000	10	40043	40043	40041	40041	40043
80024	40042	300	0	0	3	1	0	0	40028	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	0	40040	40040	29975	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	80002	0	2	80000	2	42	5020	0	14	16	17	14	40037	80000	10	40043	40041	40043	40043	40043
80024	40042	299	0	0	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40018	0	40043	40043	29975	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	62	2	80002	2	42	5021	1	17	16	17	17	40037	80000	10	40044	40044	40043	40041	40044
80024	40042	299	1	549	3	0	1	0	40027	0	16	1	25	80010	10	80000	10	80000	50	1839472	0	40018	0	40042	40042	29978	3	30023	80010	20	80000	20	240000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	42	1	80002	0	2	80002	2	42	5021	1	17	16	17	17	40039	80000	10	40044	40044	40041	40043	40044
80024	40042	300	1	0	3	0	1	0	40027	16	0	1	25	80010	10	80000	10	80000	50	1839448	0	40017	0	40042	40042	29975	3	30023	80010	20	80000	20	240000	40043	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	2	80002	2	42	5021	1	17	16	17	16	40040	80000	10	40044	40041	40043	40044	40043

STR (register, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations