Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STR (register, lsl, D)

Test 1: uops

Code:

  str d0, [x6, x7, lsl #3]
  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)031e3f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a7a8afcfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
1005540405252510001000100022352515540540353340610001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353340610001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353339810001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353340510001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353340510001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353339810001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353339810001000300054054011100110001000100010000100073216225371000541541541541541
1004540495252510001000100022352515540540353339810001000300054054011100110001000100010000100073216225371000541541541541541
1004540405252510001000100022352515540540353339810001000300054054011100110001000100010000100073216225371000541541541541541
1004540305252510001000100022352515540540353339810001000300054054011100110001000100010000100073216225371000541541541541541

Test 2: throughput

Count: 8

Code:

  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)0305080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a4a6a7a8a9acafbcdtlb miss (c1)c2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
80205400473001110001414003202580100100800001008000650018397181400224004840047299667299998010620080016200240048400474004711802011009910010080000800001008001415018001401178000014140111511811600400440800001004004840048400484004840048
80204400473001100001414017302580100100800001008000650018397181400224004740047299667299998010620080016200240048400474004711802011009910010080000800001008001414018001400148000014141111511801600400440800001004004840048400494004840048
802044004730010100014140032025801001008000010080006500183971814002240047400472996672999980106200800162002400484004740047118020110099100100800008000010080015160180014111480000141462225332141281515417452800001004004840048400484004841856
8020440325311122143933107114003202580100100800001008000050018395941400224004740047299496299938010020080000200240000400474004811802011009910010080000800001008001415008001400148000014141111512022422400440800001004004840048400484004840048
80204400473001110001414003202580100100800001008000050018395951400234004740047299496299938010020080000200240000400474004711802011009910010080000800001008001414028001401148000014142111512022422400440800001004004840048400494004840048
80204400473001110001514003202580100100800001008000050018395940400234004740047299496299938010020080000200240000400474004711802011009910010080000800001008001414018001401148000014141111512022422400440800001004004840048400484004840049
802044004730010100012214003202580100100800001008000050018396050400234004740047299496299938010020080000200240000400474004711802011009910010080000800001008001414018001400208000014141111512022422400440800001004004940048400484004840048
80204400473001010001414003222580100100800001008000050018395941400224004740047299496299938010020080000200240000400474004711802011009910010080000800001008001514008001400158000014142111512022422400440800001004004840048400494004840048
80204400473001100001414003202580100100800001008000050018395940400224004740047299496299938010020080000200240000400474004711802011009910010080000800001008001514008001400158000014141111512022422400440800001004004840048400484004840048
80204400473001010001414003202580100100800001008000050018395950400224004740047299496299938010020080000200240000400474004711802011009910010080000800001008001514008001400148000014140111512022422400440800001004004840048400484004840049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307081e223f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a6a7a8acafc2branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
800254004030000004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020201610124003780000104004140041400414004140041
800244004030000004002525800101080000108000050183935214001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020111611154003780000104004140041400414004140041
800244004030000004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020111611114003780000104004140041400414004140041
800244004030000004002525800101080000108000050183935214001540040400402997533002780010208000020240000400404004011800211091010800008000010800000800000080000005020131613114003780000104004140041400414004140041
800244004030000004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020111611114003780000104004140204401904004140041
800244004030000004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020121611114003780000104018040041400414004140041
800244004030000004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020111611124003780000104004140041400414004140041
800244004030000004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800001080000005020111611144003780000104004140041400414004140041
800244004030100004002525800101080000108000050183935204001540040400402997533002080010208000020240000400404004011800211091010800008000010800000800000080000005020111612124003780000104004140041400414004140041
80024400402990000400252580010108000010800005018393520400154004040040299753300208001020800002024000040040400401180021109101080000800001080000080000008000000503811168124003780000104004140041400414004140041