Firestorm: STR (register, lsl, D) measurements

Code:

  str d0, [x6, x7, lsl #3]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	af	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	406	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	406	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	405	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	405	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	9	525	25	1000	1000	1000	22352	515	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	4	0	525	25	1000	1000	1000	22352	515	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541
1004	540	3	0	525	25	1000	1000	1000	22352	515	540	540	353	3	398	1000	1000	3000	540	540	1	1	1001	1000	1000	1000	1000	0	1000	73	2	16	2	2	537	1000	541	541	541	541	541

Count: 8

Code:

  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40047	300	1	1	1	0	0	0	14	1	40032	0	25	80100	100	80000	100	80006	500	1839718	1	40022	40048	40047	29966	7	29999	80106	200	80016	200	240048	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	1	80014	0	1	17	80000	14	14	0	1	1	1	5118	1	16	0	0	40044	0	80000	100	40048	40048	40048	40048	40048
80204	40047	300	1	1	0	0	0	0	14	1	40173	0	25	80100	100	80000	100	80006	500	1839718	1	40022	40047	40047	29966	7	29999	80106	200	80016	200	240048	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	1	80014	0	0	14	80000	14	14	1	1	1	1	5118	0	16	0	0	40044	0	80000	100	40048	40048	40049	40048	40048
80204	40047	300	1	0	1	0	0	0	14	1	40032	0	25	80100	100	80000	100	80006	500	1839718	1	40022	40047	40047	29966	7	29999	80106	200	80016	200	240048	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	16	0	1	80014	1	1	14	80000	14	14	6	2	2	2	5332	14	128	15	15	41745	2	80000	100	40048	40048	40048	40048	41856
80204	40325	311	1	2	2	14	3	933	1071	1	40032	0	25	80100	100	80000	100	80000	500	1839594	1	40022	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40048	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	0	80014	0	0	14	80000	14	14	1	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40048	40048	40048	40048
80204	40047	300	1	1	1	0	0	0	14	1	40032	0	25	80100	100	80000	100	80000	500	1839595	1	40023	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	2	80014	0	1	14	80000	14	14	2	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40048	40049	40048	40048
80204	40047	300	1	1	1	0	0	0	15	1	40032	0	25	80100	100	80000	100	80000	500	1839594	0	40023	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	1	80014	0	1	14	80000	14	14	1	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40048	40048	40048	40049
80204	40047	300	1	0	1	0	0	0	122	1	40032	0	25	80100	100	80000	100	80000	500	1839605	0	40023	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	1	80014	0	0	20	80000	14	14	1	1	1	1	5120	2	24	2	2	40044	0	80000	100	40049	40048	40048	40048	40048
80204	40047	300	1	0	1	0	0	0	14	1	40032	2	25	80100	100	80000	100	80000	500	1839594	1	40022	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	14	0	0	80014	0	0	15	80000	14	14	2	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40048	40049	40048	40048
80204	40047	300	1	1	0	0	0	0	14	1	40032	0	25	80100	100	80000	100	80000	500	1839594	0	40022	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	14	0	0	80014	0	0	15	80000	14	14	1	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40048	40048	40048	40048
80204	40047	300	1	0	1	0	0	0	14	1	40032	0	25	80100	100	80000	100	80000	500	1839595	0	40022	40047	40047	29949	6	29993	80100	200	80000	200	240000	40047	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	14	0	0	80014	0	0	14	80000	14	14	0	1	1	1	5120	2	24	2	2	40044	0	80000	100	40048	40048	40048	40048	40049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	1e	22	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	20	16	10	12	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	1	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	11	16	11	15	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	11	16	11	11	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	1	40015	40040	40040	29975	3	30027	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	13	16	13	11	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	11	16	11	11	40037	80000	10	40041	40204	40190	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	12	16	11	11	40037	80000	10	40180	40041	40041	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	11	16	11	12	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	300	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	1	0	80000	0	0	5020	11	16	11	14	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	301	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5020	11	16	12	12	40037	80000	10	40041	40041	40041	40041	40041
80024	40040	299	0	0	0	0	40025	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	80000	0	0	80000	0	0	5038	11	16	8	12	40037	80000	10	40041	40041	40041	40041	40041

STR (register, lsl, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations