Firestorm: STR (register, lsl, Q) measurements

Code:

  str q0, [x6, x7, lsl #4]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	st unit uop (a7)	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2006	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	0	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	545
2004	542	4	0	0	1	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	1	517	542	542	230	3	278	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543
2004	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	1	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543
2004	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	0	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543
2004	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	0	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	2	0	73	1	16	1	1	539	1000	1000	1000	546	543	543	543	543
2004	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	0	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543
2004	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	1	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	545	543	543	543	543
2004	542	4	0	0	0	0	527	16	0	25	2000	1000	1000	1000	1000	5000	22488	0	517	542	544	232	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543
2004	542	4	0	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	0	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543
2004	542	4	3	0	0	0	527	0	0	25	2000	1000	1000	1000	1000	5000	22488	1	517	542	542	230	3	275	2000	1000	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	1000	1000	0	0	73	1	16	1	1	539	1000	1000	1000	543	543	543	543	543

Count: 8

Code:

  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160206	40042	299	1	1	402	0	1	40027	0	16	0	25	160112	80108	80000	80116	80006	400552	1839639	1	40017	40042	40042	19963	6	19993	160118	80216	80016	80216	240048	40044	40044	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	80000	2	42	1	1	1	5117	1	16	1	1	40041	80008	80000	80100	40045	40043	40043	40043	40045
160204	40056	300	1	1	717	3	1	40027	16	16	1	25	160108	80108	80000	80112	80006	400552	1839514	1	40019	40042	40044	19961	6	19993	160118	80216	80016	80216	240048	40042	40044	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	80000	0	42	1	1	1	5117	1	16	1	1	40039	80008	80000	80100	40043	40043	40043	40043	40043
160204	40042	300	1	1	741	3	0	40029	0	0	1	25	160108	80108	80000	80116	80006	400568	1839620	1	40017	40042	40042	19968	6	19994	160118	80216	80016	80216	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	80002	0	0	1	1	1	5117	1	16	1	1	40039	80008	80000	80100	40043	40043	40043	40045	40043
160204	40044	300	1	1	24	3	0	40029	0	0	0	25	160108	80108	80000	80112	80006	400552	1839514	1	40017	40042	40042	19967	6	19993	160124	80216	80016	80216	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	80000	0	42	1	1	1	5117	1	16	1	1	40041	80012	80000	80100	40043	40043	40271	40268	40043
160204	40042	300	1	1	12	0	0	40027	0	16	0	25	160108	80108	80000	80112	80006	400552	1839514	1	40017	40042	40042	19959	6	19993	160118	80216	80016	80336	240048	40042	40044	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	80000	2	0	1	1	1	5117	1	16	1	1	40039	80012	80000	80100	40043	40043	40043	40043	40045
160204	40185	299	1	1	33	0	0	40027	0	0	0	25	160108	80108	80000	80112	80008	400552	1839620	1	40017	40042	40042	19961	6	19993	160118	80216	80016	80216	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	80000	0	42	1	1	1	5117	1	16	1	1	40039	80012	80000	80100	40043	40043	40043	40045	40043
160204	40042	300	1	1	528	3	0	40027	0	16	1	25	160108	80108	80000	80112	80006	400552	1839514	1	40017	40042	40042	19969	6	19993	160119	80216	80136	80216	240048	40042	40044	1	1	80201	100	99	100	100	80000	80000	100	80062	42	0	80002	0	3	80002	0	0	1	1	1	5117	1	16	1	1	40041	80012	80000	80100	40043	40043	40043	40043	40043
160204	40042	300	1	1	57	0	0	40027	0	0	0	25	160112	80108	80000	80112	80008	400552	1839514	1	40017	40042	40042	19967	6	19995	160118	80216	80016	80216	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	80000	2	0	1	1	1	5117	1	16	1	1	40039	80012	80000	80100	40043	40043	40043	40043	40045
160204	40042	300	1	1	48	0	0	40029	0	0	0	25	160112	80108	80000	80112	80006	400552	1839514	1	40019	40044	40042	19967	6	19996	160118	80216	80016	80216	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	1	0	80002	0	0	1	1	1	5117	1	16	1	1	40039	80012	80000	80100	40043	40259	40045	40045	40043
160204	40044	300	1	1	327	0	0	40027	16	16	0	25	160108	80108	80000	80112	80008	400552	1839514	0	40019	40042	40042	19962	6	19993	160118	80216	80016	80216	240048	40044	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	1	0	80000	0	42	1	1	1	5117	1	16	1	1	40039	80008	80000	80100	40043	40043	40045	40057	40045

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160026	40061	310	1	0	1	0	0	0	0	27	0	1	0	0	40027	16	16	0	25	160010	80010	80000	80010	80000	400050	1839560	1	40017	40042	40042	19978	0	3	20024	160010	80158	80000	80020	240000	40051	40044	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	1	0	5	80002	2	34	0	0	5020	0	0	11	16	7	11	40039	80000	80000	80010	40052	40043	40045	40043	40053
160024	40042	300	0	0	0	0	0	0	0	429	6	1	0	0	40029	16	16	0	25	160010	80010	80000	80010	80000	400050	1839488	0	40017	40042	40042	19978	0	3	20024	160010	80020	80000	80020	240000	40044	40053	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	0	80000	2	34	0	0	5020	0	0	12	16	12	12	40041	80000	80000	80010	40054	40043	40053	40045	40043
160024	40042	300	0	0	0	0	0	0	0	885	0	0	0	0	40027	0	0	0	25	160010	80010	80000	80010	80000	400050	1839488	1	40017	40042	40042	19978	0	3	20022	160010	80020	80000	80020	240000	40044	40044	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	5	80002	2	34	0	0	5020	0	0	6	16	11	10	40041	80000	80000	80010	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	33	14	0	0	1	40034	0	0	0	25	160010	80010	80000	80010	80000	400050	1839824	0	40024	40063	40053	19985	0	3	20022	160010	80020	80000	80020	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	15	0	8	80000	2	0	0	0	5020	0	0	9	16	11	11	40041	80000	80000	80010	40043	40043	40043	40043	40043
160024	40044	300	0	0	0	0	0	0	0	0	0	0	0	0	40027	16	16	0	25	160010	80010	80000	80010	80000	400050	1839560	1	40019	40042	40042	19979	0	3	20022	160010	80020	80000	80020	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80001	0	0	0	0	80000	0	0	0	80000	2	34	0	0	5020	0	0	9	16	12	12	40039	80000	80000	80010	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	549	0	1	0	0	40029	16	16	0	25	160010	80010	80000	80010	80000	400050	1839488	0	40027	40042	40044	19979	0	3	20024	160010	80020	80000	80020	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	5020	0	0	12	16	11	10	40228	80116	80000	80010	40045	40043	40045	40045	40043
160024	40042	300	0	0	0	0	0	0	0	813	0	0	0	0	40029	0	0	0	25	160010	80010	80000	80010	80000	400050	1839488	1	40019	40044	40042	19979	0	3	20033	160010	80020	80000	80020	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	5020	0	0	12	16	11	14	40039	80000	80000	80010	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	15	0	0	0	0	40029	0	16	0	25	160010	80010	80000	80010	80000	400050	1839488	0	40028	40042	40044	19978	0	3	20024	160010	80020	80000	80020	240000	40044	40044	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	5098	0	0	12	16	10	6	40039	80000	80000	80010	40043	40043	40043	40043	40043
160024	40042	299	0	0	0	0	0	0	0	0	0	1	0	0	40027	16	16	0	25	160010	80010	80000	80010	80000	400050	1839488	0	40017	40042	40042	19978	0	3	20027	160010	80020	80000	80020	240000	40044	40044	2	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	0	80000	0	0	0	0	5020	0	0	11	16	13	12	40039	80000	80000	80010	40043	40043	40043	40043	40043
160024	40042	300	0	0	0	0	0	0	0	915	0	0	0	0	40027	0	0	0	25	160010	80010	80000	80010	80000	400050	1839560	1	40017	40042	40042	19978	0	3	20024	160010	80020	80000	80020	240000	40053	40044	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	0	80000	0	0	0	0	5020	0	0	11	16	9	11	40039	80000	80000	80010	40043	40043	40045	40045	40043

STR (register, lsl, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations