Firestorm: STR (register, lsl, S) measurements

Code:

  str s0, [x6, x7, lsl #2]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	0	0	1	0	534	16	16	0	25	1000	1000	1000	22856	1	517	542	540	353	3	400	1000	1000	3000	551	542	1	1	1001	1000	1000	1002	34	1002	0	2	1002	2	0	73	1	16	1	1	539	1000	550	543	543	543	543
1004	542	4	0	0	6	0	0	527	16	16	0	25	1000	1000	1000	22424	0	526	542	542	355	3	408	1000	1000	3000	542	550	1	1	1001	1000	1000	1000	34	1002	0	5	1002	2	34	73	1	16	1	1	537	1000	550	551	543	543	543
1004	542	4	0	0	3	0	0	527	16	0	0	25	1000	1000	1000	22352	1	515	542	542	355	3	400	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	34	1002	0	8	1002	2	34	73	1	16	1	1	539	1000	543	551	541	543	543
1004	542	4	0	0	3	0	0	527	16	16	0	25	1000	1000	1000	22424	1	517	542	540	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	551	551
1004	551	4	0	0	0	0	0	527	16	16	0	25	1000	1000	1000	22856	1	517	542	550	353	3	408	1000	1000	3000	542	549	1	1	1001	1000	1000	1000	34	1002	0	8	1000	0	34	73	1	16	1	1	546	1000	543	543	543	551	551
1004	549	4	0	0	3	1	0	527	0	16	0	25	1000	1000	1000	22352	0	517	551	542	353	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	34	1000	0	2	1002	2	34	73	1	16	1	1	548	1000	543	543	552	552	543
1004	542	4	0	0	3	0	0	534	16	16	0	25	1000	1000	1000	22424	1	524	540	542	363	3	400	1000	1000	3000	542	549	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	550	551	543	543	543
1004	542	4	0	0	3	0	0	527	16	16	2	25	1000	1000	1000	22424	0	517	542	540	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	0	73	1	16	1	1	539	1000	543	543	543	550	551
1004	550	4	0	0	3	0	0	535	16	16	0	25	1000	1000	1000	22808	0	517	542	542	355	3	400	1000	1000	3000	549	542	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	34	73	1	16	1	1	546	1000	543	550	551	543	543
1004	542	3	0	0	3	0	0	527	16	16	2	25	1000	1000	1000	22424	1	524	542	542	363	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	34	1002	0	0	1000	2	34	73	1	16	1	1	539	1000	543	543	543	543	543

Count: 8

Code:

  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]
  str s0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40052	300	1	1	1	0	0	15	1	0	3	40037	0	16	0	25	80100	100	80000	100	80007	500	1839719	1	40015	40040	40042	29959	7	29992	80107	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	2	80002	2	34	0	0	1	1	1	5122	9	16	8	8	40039	0	80000	100	40043	40041	40041	40041	40043
80204	40042	300	0	0	0	0	0	3	1	0	2	40025	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	40015	40042	40042	29961	7	29992	80106	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	5	80002	0	34	0	0	1	1	1	5122	8	16	8	8	40047	0	80000	100	40043	40051	40043	40043	40043
80204	40042	300	0	0	0	0	0	12	1	0	2	40027	0	0	0	25	80100	100	80000	100	80007	500	1839455	1	40017	40042	40040	29969	7	29994	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	0	1	1	1	5122	8	16	8	8	40037	0	80000	100	40043	40052	40041	40051	40043
80204	40040	300	0	0	0	0	0	3	0	0	2	40027	16	16	0	25	80100	100	80060	100	80007	500	1839810	0	40025	40042	40042	29961	7	29992	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	8	80002	2	34	0	0	1	1	1	5122	8	16	8	8	40039	0	80000	100	40041	40043	40041	40043	40051
80204	40042	300	0	0	0	0	0	9	1	0	2	40025	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	40026	40042	40042	29959	7	29992	80107	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80000	0	0	8	80002	2	34	0	0	1	1	1	5122	6	16	8	8	40039	0	80000	100	40043	40050	40043	40051	40041
80204	40042	300	0	0	0	0	0	3	0	0	2	40027	16	16	0	25	80100	100	80000	100	80007	500	1839839	1	40017	40040	40042	29959	7	29994	80107	200	80016	200	240048	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	0	80002	2	34	0	0	1	1	1	5122	8	16	8	8	40039	0	80000	100	40041	40041	40043	40043	40041
80204	40040	300	0	0	0	0	0	3	1	0	2	40025	0	0	0	25	80100	100	80000	100	80006	500	1839378	0	40017	40042	40042	29961	7	30002	80107	200	80016	200	240048	40040	40051	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80000	0	0	2	80002	0	34	0	0	1	1	1	5122	8	16	9	8	40039	0	80000	100	40043	40043	40041	40041	40043
80204	40042	300	0	0	0	0	0	0	0	0	2	40027	16	0	0	25	80100	100	80000	100	80007	500	1839887	0	40015	40042	40042	29961	7	29994	80221	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	0	80000	2	34	0	0	1	1	1	5122	8	16	8	8	40039	0	80000	100	40043	40043	40041	40043	40052
80204	40042	300	0	0	0	0	0	3	0	0	2	40035	0	16	0	25	80100	100	80000	100	80006	500	1839378	0	40026	40042	40040	29961	7	29994	80106	200	80016	200	240048	40051	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80000	0	0	2	80012	2	34	0	0	1	1	1	5122	8	16	8	8	40039	0	80000	100	40041	40043	40041	40043	40041
80204	40040	299	0	0	0	0	0	9	0	0	2	40027	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	40017	40042	40048	29959	7	30002	80107	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	0	0	80002	0	0	0	80002	0	34	0	0	1	1	1	5122	8	16	8	8	40039	0	80000	100	40043	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	3	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839784	0	40015	40040	40040	29984	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	0	2	80000	2	34	5032	2	16	2	2	40039	0	80000	10	40041	40041	40051	40043	40043
80024	40040	300	0	0	0	0	3	1	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40017	40040	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	2	80002	2	34	5030	2	16	2	2	40046	0	80000	10	40050	40041	40051	40041	40041
80024	40040	300	0	0	0	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40024	40042	40042	29977	3	30031	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	0	80000	0	34	5032	2	16	2	2	40047	0	80000	10	40041	40043	40041	40043	40043
80024	40040	300	0	0	0	0	3	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40040	40042	29977	3	30022	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80000	0	0	80000	2	34	5030	2	16	2	2	40039	0	80000	10	40051	40041	40051	40043	40043
80024	40042	299	0	0	0	9	0	1	40035	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40040	29975	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80000	0	2	80002	0	0	5028	2	16	2	2	40048	0	80000	10	40043	40043	40041	40043	40041
80024	40040	300	0	0	0	0	0	1	40025	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	40015	40042	40040	29977	3	30020	80010	20	80000	20	240000	40049	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	0	8	80000	2	0	5030	2	16	2	2	40037	0	80000	10	40043	40041	40041	40041	40041
80024	40042	300	0	0	0	0	9	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839424	0	40015	40050	40042	29975	3	30022	80010	20	80000	20	240000	40049	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80002	0	2	80000	0	0	5030	3	16	2	2	40037	0	80000	10	40043	40050	40041	40043	40041
80024	40040	300	0	0	0	0	3	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	40025	40042	40042	29975	3	30031	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80000	0	0	80002	2	34	5032	2	16	2	2	40039	0	80000	10	40041	40043	40050	40043	40050
80024	40042	300	0	0	0	0	3	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	40015	40042	40042	29975	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	0	2	80002	2	0	5030	2	16	2	2	40039	0	80000	10	40043	40041	40043	40043	40043
80024	40049	300	0	0	0	0	3	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40015	40040	40042	29975	3	30030	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	80002	0	2	80002	0	0	5030	2	16	2	2	40039	0	80000	10	40043	40041	40043	40041	40043

STR (register, lsl, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations