Firestorm: STR (register, sxtw, D) measurements

Code:

  str d0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	0	1	0	527	16	16	1	25	1000	1000	1000	22472	0	518	543	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1002	0	42	73	2	16	1	1	540	1000	543	541	543	541	543
1004	542	4	9	3	1	0	528	16	16	0	25	1000	1000	1000	22448	0	517	542	542	353	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1000	2	42	73	1	16	1	1	539	1000	544	544	543	543	543
1004	542	4	0	3	0	0	528	16	16	0	25	1000	1000	1000	22352	0	517	542	542	353	3	401	1000	1000	3000	540	543	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	541
1004	542	4	0	3	0	0	528	16	0	1	25	1000	1000	1000	22448	0	517	542	543	353	3	400	1000	1000	3000	542	554	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1002	2	42	73	1	16	1	1	540	1000	541	543	543	544	544
1004	543	3	0	7	1	0	527	16	16	1	25	1000	1000	1000	22448	0	517	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	1	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	544
1004	543	4	0	7	1	0	527	16	16	1	25	1000	1000	1000	22448	0	517	542	542	356	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1000	2	42	73	1	16	1	1	539	1000	555	543	543	543	543
1004	542	5	0	3	1	0	527	16	16	1	25	1000	1000	1000	22448	0	517	542	554	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1000	0	42	73	1	16	1	1	551	1000	585	637	543	543	543
1004	542	4	0	3	0	0	539	16	16	0	25	1000	1000	1000	22448	0	515	540	542	355	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1002	2	42	73	1	16	1	1	539	1000	541	541	543	543	543
1004	542	4	0	3	0	0	527	16	16	1	25	1000	1000	1000	22448	0	517	554	542	353	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	2	1000	2	42	73	1	16	1	1	540	1000	543	543	541	543	543
1004	542	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22472	0	517	543	543	356	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	5	1002	2	42	73	1	16	1	1	539	1000	544	544	544	544	544

Count: 8

Code:

  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]
  str d0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	300	1	0	0	1	0	0	0	18	0	0	1	40039	16	16	3	25	80100	100	80000	100	80007	500	1839718	0	40038	40053	40054	29973	7	30006	80106	200	80016	200	240048	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	14	44	0	0	80016	2	1	16	80002	16	44	14	0	1	1	1	5118	16	40051	80000	100	40055	40053	40054	40061	40054
80204	40054	299	1	0	0	1	0	0	0	17	1	0	1	40032	16	16	6	25	80100	100	80000	100	80007	500	1840054	0	40027	40054	40054	29973	7	30000	80107	200	80016	200	240048	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	44	0	1	80016	2	0	24	80000	16	44	14	0	1	1	1	5118	16	40044	80000	100	40193	40053	40058	40064	40053
80204	40202	301	1	0	2	0	1	0	6	371	1	0	1	40039	16	16	2	25	80100	100	80000	100	80006	500	1839987	0	40029	40052	40047	29972	7	30006	80106	200	80016	200	240048	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80077	14	44	0	1	80016	1	1	874	80002	14	44	14	0	1	1	1	5118	16	40051	80000	100	40055	40053	40054	40065	40053
80204	40054	300	1	1	1	1	0	0	6	18	0	0	1	40039	16	16	2	25	80100	100	80000	100	80006	500	1840035	0	40038	40053	40054	29973	7	30006	80106	200	80016	200	240048	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80016	14	46	0	1	80016	0	0	19	80002	16	42	14	2	1	1	1	5118	16	40051	80000	100	40054	40055	40058	40055	40055
80204	40054	300	1	0	0	1	0	0	0	19	1	0	1	40039	15	0	2	25	80100	100	80000	100	80007	500	1840035	0	40029	40047	40054	29973	7	30006	80106	200	80016	200	240048	40053	40054	1	1	80201	100	99	100	100	80000	80000	100	80016	14	44	0	2	80016	1	1	23	80002	16	0	14	2	1	1	1	5118	16	40044	80000	100	40055	40053	40073	40064	40053
80204	40054	300	1	1	0	0	0	0	0	15	0	0	1	40038	16	0	1	25	80100	100	80000	100	80007	500	1840054	0	40027	40054	40054	29973	7	30015	80106	200	80016	200	240048	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	17	44	0	1	80016	0	0	19	80062	16	0	14	0	1	1	1	5118	16	40049	80000	100	40053	40055	40203	40055	40191
80204	40052	299	1	2	1	2	0	2	0	20	0	0	1	40032	0	15	1	25	80100	100	80000	100	80006	500	1840054	0	40023	40054	40054	29973	7	30006	80106	200	80016	200	240048	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80016	15	44	0	0	80016	4	1	17	80002	14	44	14	1	1	1	1	5118	16	40049	80000	100	40055	40055	40055	40054	40055
80204	40051	300	1	1	1	1	0	0	0	18	0	0	1	40039	16	16	3	25	80100	100	80000	100	80006	500	1839718	0	40027	40054	40054	29973	7	30015	80107	200	80016	200	240048	40047	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	1	80016	0	0	16	80002	16	44	14	1	1	1	1	5118	16	40044	80000	100	40055	40053	40058	40065	40053
80204	40054	300	1	0	1	0	0	0	0	21	1	0	1	40039	0	16	3	25	80100	100	80000	100	80007	500	1839959	0	40029	40063	40052	29971	7	30006	80107	200	80016	200	240048	40063	40051	1	1	80201	100	99	100	100	80000	80000	100	80015	16	0	0	1	80016	0	0	21	80000	16	44	14	2	1	1	1	5118	16	40051	80000	100	40053	40055	40068	40056	40055
80204	40047	300	1	1	1	0	0	0	0	21	0	0	1	40039	16	16	4	25	80100	100	80000	100	80007	500	1839959	0	40029	40063	40053	29971	7	29999	80107	200	80016	200	240048	40063	40047	1	1	80201	100	99	100	100	80000	80000	100	80016	14	0	0	1	80016	0	0	14	80002	16	44	14	2	1	1	1	5118	16	40052	80000	100	40055	40053	40065	40055	40053

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	3	0	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839352	1	40017	40040	40042	29977	3	30022	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	2	80002	2	34	0	5020	0	23	16	22	22	40048	0	80000	10	40043	40181	40180	40043	40182
80024	40319	311	0	0	0	0	0	0	3	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40017	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	11	80002	2	34	0	5020	0	22	16	11	22	40039	0	80000	10	40043	40052	40043	40051	40043
80024	40040	299	0	0	0	0	0	0	3	1	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839472	1	40017	40042	40042	29977	3	30022	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	8	80000	2	34	0	5020	0	9	16	22	22	40039	0	80000	10	40041	40041	40041	40052	40043
80024	40042	299	0	0	0	0	0	156	6	1	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839808	1	40024	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	1	0	0	80000	0	0	0	5020	0	22	16	22	11	40047	0	80000	10	40202	40043	40043	40041	40041
80025	40050	299	0	0	0	0	0	0	0	1	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40015	40049	40049	29985	3	30022	80010	20	80000	20	240000	40050	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	0	80002	2	0	0	5020	0	22	16	9	22	40039	0	80000	10	40043	40043	40043	40043	40041
80024	40042	300	0	0	0	0	0	0	0	0	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839856	1	40026	40042	40042	29975	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	5	80002	2	34	0	5020	0	22	16	11	22	40039	0	80000	10	40041	40050	40043	40043	40043
80024	40042	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	1	40015	40042	40040	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	8	80000	2	0	0	5020	0	22	16	11	22	40037	0	80000	10	40043	40043	40041	40043	40041
80024	40049	299	0	0	0	0	0	0	6	0	0	0	0	40035	16	16	0	370	80610	12	80600	10	81080	50	1887826	1	40607	41418	41290	30813	198	31747	80982	20	81815	20	245808	42086	41847	14	1	80021	10	9	10	10	80000	80000	10	80902	0	34	433	3	81022	0	2	12578	80962	2	34	0	5333	0	29	96	22	32	41462	0	80000	10	42261	41570	42112	42319	42251
80024	42544	316	2	1	1	17	17	2253	1587	1	0	0	1	42372	16	0	1049	565	81090	10	81020	10	81620	50	1908742	1	41318	40040	40049	29985	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	32	80002	2	0	0	5020	0	10	16	11	22	40039	0	80000	10	40043	40050	40043	40051	40043
80024	40042	300	0	0	0	0	0	0	3	0	0	0	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839424	1	40015	40042	40049	29975	3	30029	80010	20	80000	20	240420	40042	40051	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	150	80002	2	34	0	5020	0	22	16	19	9	40047	0	80000	10	40041	40051	40043	40043	40043

STR (register, sxtw, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations