Firestorm: STR (register, sxtw, Q) measurements

Code:

  str q0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	7	1	528	16	16	1	25	1000	1000	1000	22472	0	517	543	540	355	3	412	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	1002	0	2	1002	2	42	73	1	16	1	1	537	1000	541	543	544	543	543
1004	542	4	0	3	0	528	16	0	0	25	1000	1000	1000	22472	0	515	543	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	44	1002	0	2	1002	2	42	73	1	16	1	1	540	1000	544	544	543	543	543
1004	554	4	0	3	1	527	16	0	0	25	1000	1000	1000	22448	0	517	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	1002	0	2	1002	2	42	73	1	16	1	1	540	1000	543	543	555	555	543
1004	542	4	0	3	0	527	0	16	0	25	1000	1000	1000	22448	1	517	542	543	356	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	44	1002	0	2	1002	2	42	73	1	16	1	1	540	1000	543	543	564	564	543
1004	542	4	0	3	0	527	16	16	1	25	1000	1000	1000	22472	0	518	543	543	353	3	400	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	44	1000	0	2	1002	2	42	73	1	16	1	1	539	1000	544	544	555	543	543
1004	542	4	0	3	0	527	0	16	5	25	1000	1000	1000	22448	0	517	542	540	355	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	44	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	555	543	555	548	543
1004	542	3	0	3	0	527	16	0	0	25	1000	1000	1000	22448	1	517	543	543	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	44	1002	0	2	1000	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	1	527	16	16	1	25	1000	1000	1000	22448	0	517	542	554	355	3	398	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	44	1002	0	23	1002	0	42	73	1	16	1	1	539	1000	543	543	555	555	541
1004	542	4	0	3	0	527	16	16	1	25	1000	1000	1000	22472	0	517	543	543	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	1002	0	2	1002	2	42	73	1	16	1	1	537	1000	543	543	555	555	543
1004	542	4	0	3	0	525	16	16	0	25	1000	1000	1000	22448	0	517	542	554	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	44	1002	0	2	1002	2	42	73	1	16	1	1	537	1000	543	555	555	564	541

Count: 8

Code:

  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	3	1	40027	0	0	4	25	80100	100	80000	100	80006	500	1839455	0	40026	40042	40042	29961	7	29992	80107	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	2	80002	2	34	1	1	1	5118	2	16	3	3	40048	80000	100	40043	40041	40043	40043	40051
80204	40040	300	0	3	3	0	40034	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	40015	40042	40042	29961	7	30001	80106	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80002	0	34	1	1	1	5118	5	16	4	4	40039	80000	100	40043	40043	40043	40043	40051
80204	40042	299	0	0	0	1	40025	16	0	0	25	80100	100	80000	100	80006	500	1839455	0	40015	40040	40040	29961	7	29992	80106	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	5	80000	0	34	1	1	1	5118	4	16	3	3	40039	80000	100	40052	40043	40041	40043	40052
80204	40042	300	0	0	9	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	40015	40040	40042	29961	7	30003	80106	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80000	0	34	1	1	1	5118	4	16	4	4	40048	80000	100	40043	40043	40041	40041	40041
80204	40040	300	0	0	3	1	40027	16	0	0	25	80100	100	80000	100	80007	500	1839455	1	40015	40050	40042	29961	7	29994	80107	200	80016	200	240048	40050	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	2	80000	2	34	1	1	1	5118	4	16	4	3	40047	80000	100	40041	40043	40041	40043	40041
80204	40042	299	0	0	0	1	40034	16	16	0	25	80100	100	80000	100	80006	500	1839455	1	40017	40042	40049	29961	7	29992	80106	200	80016	200	240048	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80000	2	34	1	1	1	5118	3	16	3	4	40046	80000	100	40050	40041	40051	40041	40043
80204	40042	299	0	0	0	0	40035	16	0	0	25	80100	100	80000	100	80007	500	1839455	0	40026	40042	40040	29961	7	29994	80107	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	2	80000	2	34	1	1	1	5118	3	16	3	4	40037	80000	100	40043	40041	40043	40051	40043
80204	40049	299	0	0	9	1	40025	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	40017	40040	40040	29961	23	29992	80107	200	80016	200	240048	40050	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	8	80002	2	0	1	1	1	5118	2	16	3	4	40039	80000	100	40041	40041	40041	40041	40043
80204	40040	300	0	0	9	0	40027	0	16	0	25	80100	100	80000	100	80007	500	1839455	0	40015	40042	40042	29961	7	29994	80106	200	80016	200	240048	40051	40050	1	1	80201	100	99	100	100	80000	80000	100	80000	0	80002	0	2	80002	2	0	1	1	1	5118	4	16	4	4	40037	80000	100	40043	40043	40043	40043	40041
80204	40042	300	0	0	0	1	40027	16	16	0	25	80100	100	80000	100	80006	500	1839378	0	40017	40051	40042	29969	7	29992	80107	200	80016	200	240048	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80002	0	34	1	1	1	5118	4	16	4	4	40048	80000	100	40043	40043	40043	40041	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40054	300	1	0	0	0	17	0	0	1	40040	16	16	5	25	80010	10	80000	10	80000	50	1840004	0	0	40028	40054	40063	29989	3	30043	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	10	80000	80000	10	80014	16	44	0	1	80016	0	1	17	80002	16	44	14	1	5020	3	16	1	1	40061	80000	10	40048	40053	40055	40052	40055
80024	40047	300	1	1	0	0	17	0	0	1	40042	16	16	2	25	80010	10	80000	10	80000	50	1840004	3	0	40029	40052	40054	29989	3	30027	80010	20	80000	20	240000	40053	40047	1	1	80021	10	9	10	10	80000	80000	10	80015	16	44	0	0	80016	0	2	16	80002	16	0	14	1	5020	1	16	1	1	40049	80000	10	40055	40053	40055	40053	40055
80024	40052	300	1	1	1	0	14	1	0	1	40032	15	0	2	25	80010	10	80000	10	80000	50	1840004	0	0	40028	40054	40063	29989	3	30031	80010	20	80000	20	240000	40054	40063	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	0	80002	2	42	0	0	5020	1	16	1	1	40039	80000	10	40055	40053	40055	40048	40055
80024	40052	300	1	0	0	0	19	0	0	1	40048	16	0	1	25	80010	10	80000	10	80000	50	1840004	0	0	40022	40052	40054	29989	3	30034	80010	20	80000	20	240000	40053	40047	1	1	80021	10	9	10	10	80000	80000	10	80015	14	0	0	1	80016	0	1	19	80002	16	0	14	2	5020	1	16	1	1	40060	80000	10	40055	40052	40055	40048	40055
80024	40047	300	1	1	1	99	17	1	0	1	40042	0	0	0	25	80010	10	80000	10	80000	50	1839934	0	0	40029	40064	40052	29987	3	30034	80010	20	80000	20	240000	40048	40052	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	60	0	5	80002	2	42	0	0	5020	1	16	1	1	40039	80000	10	40043	40041	40043	40043	40044
80024	40042	300	0	0	0	0	3	0	0	0	40033	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	0	40015	40040	40040	29977	3	30022	80010	20	80000	20	240000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80000	2	42	0	0	5020	1	16	1	1	40039	80000	10	40043	40044	40044	40043	40041
80024	40042	300	0	0	0	0	3	0	0	0	40028	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80015	16	42	0	1	80076	0	1	2	80002	2	42	0	0	5020	1	16	1	1	40039	80000	10	40055	40064	40055	40053	40053
80024	40054	300	1	1	0	0	20	0	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839472	0	0	40018	40043	40042	29978	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5020	1	16	1	1	40039	80000	10	40043	40043	40041	40043	40043
80024	40042	300	0	0	0	0	3	0	0	0	40040	0	0	0	25	80010	10	80000	10	80000	50	1839908	0	0	40029	40052	40047	29987	3	30034	80010	20	80000	20	240000	40047	40053	1	1	80021	10	9	10	10	80000	80000	10	80016	16	44	1	0	80016	0	0	19	80000	14	0	14	1	5020	1	16	1	1	40051	80000	10	40041	40044	40041	40043	40044
80024	40042	299	0	0	0	0	3	1	0	0	40050	16	16	2	25	80010	10	80000	10	80000	50	1840508	0	0	40029	40054	40063	29999	3	30032	80010	20	80000	20	240000	40047	40048	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5020	1	16	1	1	40039	80000	10	40065	40055	40064	40055	40055

STR (register, sxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations