Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STR (register, sxtw, S)

Test 1: uops

Code:

  str s0, [x6, w7, sxtw]
  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)031f223f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a2a7acafbcdcache store miss (c0)cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
1005542460527161602510001000100022424051754255035534001000100030005425511110011000100010003410022100223473116115471000543543551550543
1004542430535161602510001000100022424051754254235534001000100030005425421110011000100010003410022100223473116115471000543543551552552
1004542431527161602510001000100022424051754254236334001000100030005495421110011000100010003410022100223473116115391000543543543543551
1004551430527161602510001000100022424051754254035534001000100030005425511110011000100010003410028100223473116115391000550551543543543
1004542431527161602510001000100022424051754254935534001000100030005425511110011000100010003410025100223473116115391000550551543543543
1004542430527161602510001000100022424051755054235534001000100030005425491110011000100010003410028100223473116115391000543551550543543
1004542531527161602510001000100022424051755054235534001000100030005425501110011000100010003410028100223473116115391000543543543551551
1004549431527161602510001000100022424051755054235534001000100030005425501110011000100010003410028100223473116115391000551552543543543
1004542491534161602510001000100022424051754254236234001000100030005425421110011000100010003410025100223473116115391000551550543543543
1004542430534161602510001000100022832051754255035534071000100030005425491110011000100010003410028100223473116115471000543543550551550

Test 2: throughput

Count: 8

Code:

  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire (01)cycle (02)0305080b18191e1f2223243a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
8020540052300101000180001400321616025801001008000010080006500183971804002204004740059299717300118010720080016200240048400504005211802011009910010080000800001008001416360080016011480002163614011151180160040049800001004006140059400504006040060
8020440059300111000141001400331616825801001008000010080006500184024614003404004740047299697299998010620080016200240048400604005211802011009910010080000800001008001415360180016002180002163614111151180160040055800001004005440058400534004840048
802044004730010100019100140032161602580100100800001008000650018402940400340400504005229966730010801062008001620024004840047400531180201100991001008000080000100800151536008001401148000216014011151180160040048800001004006240059400484006040058
802044005230010100014000140033161611258010010080000100800075001840275140028040058400582996773000380106200800162002400484005840060118020110099100100800008000010080015150028001400178000016014011151180160040049800001004004840048400534005940061
802044005830011200014100140046016525801001008000010080006500184027704002304004740047299717299998010620080016200240048400524005211802011009910010080000800001008001516360180014021480002163614211151180160040057800001004004840053400494005440060
80204400523001000001410014003201602580100100800001008000750018402750401170400504005229970730010801062008001620024004840051400531180201100991001008000080000100800151636018001601148000014014011151180160040056800001004005340048400484004840048
802044005730011100020100140032161602580100100800001008000650018398620400220400584005829976730003801062008001620024004840058400471180201100991001008000080000100800141434008001600178000214014011151180160040056800001004004840060400544004940049
802044005230010100019000140044016025801001008000010080007500183971814002604005840058299787300128010620080016200240048400584004811802011009910010080000800001008001414360080014001480002143614111151180160040049800001004005340048400484004940051
802044005930010000014000140032161652580100100800001008000650018402460400340400514004729966730004801062008001620024004840047400521180201100991001008000080000100800161536208001602148000216014111151180160040055800001004004840053400604005440060
802044005229911000018100140032016025801001008000010080006500184034214002804005840060299777299998010620080016200240048400484006011802011009910010080000800001008001414362180016011880002163614111151180160040044800001004004840048400584005340059

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f22233f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a2a7a8acafbcdcache store miss (c0)cdcfd0d5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
80025400423000018310400350160258001010800001080000501839424400174005240042299773300228001020800002024000040042400421180021109101080000800001080000348000202800022340502001316224003980000104005140043400504004340050
80024400423000048010400251616225800101080000108000050183976040017400424004229977330020800102080000202400004004240040118002110910108000080000108000034800020280000234050200216634003980000104027440328400434005240193
8002440042302007293004002716160258001010800001080000501839424400174004940042299773300228001020800002024000040050400421180021109101080000800001080000348006201480062234050200216224003980000104004340043400434004340052
80024400423000012300400351616025800101080000108000050183942440025402134020929980330022800102080000202400004004240042118002110910108000080000108000034800020280002234050200616634003980000104004340052400434005240043
8002440051299003931040027161602580010108000010800005018394244001740052400402997733003080010208000020240000400424004211800211091010800008000010800003480002008000200050200216234003980000104005240043400524004340043
80024400422990087300400271616025800101080000108000050183985640017400424004429977330029800102080000202400004004240049118002110910108000080000108000034800020280002234050200216264003980000104004340050400434005140043
8002440042300014291004002716168425800101080060108000050183942440015400434004029977330146800102080000202400004004240050118002110910108000080000108000034800020080002234050200224224003980000104004340051400434005140043
800244004930000330040027161602580010108000010800005018394244001740042400422997733003080010208000020240000400424004211800211091010800008000010800003480002028000220050200216224003780000104005140043400514004340043
800244004229900391040027160025800101080000108000050183942440017400454004529984330022800102080000202400004005040042118002110910108000080000108000034800020080002234050200216264003980000104004340043400414005240043
80024400423000027600400361616025800101080000108000050183942440017400514004229985330022800102080000202400004005040042118002110910108000080000108000034800000580002234050200616564003980000104004340043400434004340051