Firestorm: STR (register, sxtw, S) measurements

Code:

  str s0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	6	0	527	16	16	0	25	1000	1000	1000	22424	0	517	542	550	355	3	400	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	1	16	1	1	547	1000	543	543	551	550	543
1004	542	4	3	0	535	16	16	0	25	1000	1000	1000	22424	0	517	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	1	16	1	1	547	1000	543	543	551	552	552
1004	542	4	3	1	527	16	16	0	25	1000	1000	1000	22424	0	517	542	542	363	3	400	1000	1000	3000	549	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	551
1004	551	4	3	0	527	16	16	0	25	1000	1000	1000	22424	0	517	542	540	355	3	400	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	1	16	1	1	539	1000	550	551	543	543	543
1004	542	4	3	1	527	16	16	0	25	1000	1000	1000	22424	0	517	542	549	355	3	400	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	34	1002	5	1002	2	34	73	1	16	1	1	539	1000	550	551	543	543	543
1004	542	4	3	0	527	16	16	0	25	1000	1000	1000	22424	0	517	550	542	355	3	400	1000	1000	3000	542	549	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	1	16	1	1	539	1000	543	551	550	543	543
1004	542	5	3	1	527	16	16	0	25	1000	1000	1000	22424	0	517	550	542	355	3	400	1000	1000	3000	542	550	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	1	16	1	1	539	1000	543	543	543	551	551
1004	549	4	3	1	527	16	16	0	25	1000	1000	1000	22424	0	517	550	542	355	3	400	1000	1000	3000	542	550	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	1	16	1	1	539	1000	551	552	543	543	543
1004	542	4	9	1	534	16	16	0	25	1000	1000	1000	22424	0	517	542	542	362	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	5	1002	2	34	73	1	16	1	1	539	1000	551	550	543	543	543
1004	542	4	3	0	534	16	16	0	25	1000	1000	1000	22832	0	517	542	550	355	3	407	1000	1000	3000	542	549	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	1	16	1	1	547	1000	543	543	550	551	550

Count: 8

Code:

  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]
  str s0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40052	300	1	0	1	0	0	0	18	0	0	0	1	40032	16	16	0	25	80100	100	80000	100	80006	500	1839718	0	40022	0	40047	40059	29971	7	30011	80107	200	80016	200	240048	40050	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	16	36	0	0	80016	0	1	14	80002	16	36	14	0	1	1	1	5118	0	16	0	0	40049	80000	100	40061	40059	40050	40060	40060
80204	40059	300	1	1	1	0	0	0	14	1	0	0	1	40033	16	16	8	25	80100	100	80000	100	80006	500	1840246	1	40034	0	40047	40047	29969	7	29999	80106	200	80016	200	240048	40060	40052	1	1	80201	100	99	100	100	80000	80000	100	80014	15	36	0	1	80016	0	0	21	80002	16	36	14	1	1	1	1	5118	0	16	0	0	40055	80000	100	40054	40058	40053	40048	40048
80204	40047	300	1	0	1	0	0	0	19	1	0	0	1	40032	16	16	0	25	80100	100	80000	100	80006	500	1840294	0	40034	0	40050	40052	29966	7	30010	80106	200	80016	200	240048	40047	40053	1	1	80201	100	99	100	100	80000	80000	100	80015	15	36	0	0	80014	0	1	14	80002	16	0	14	0	1	1	1	5118	0	16	0	0	40048	80000	100	40062	40059	40048	40060	40058
80204	40052	300	1	0	1	0	0	0	14	0	0	0	1	40033	16	16	11	25	80100	100	80000	100	80007	500	1840275	1	40028	0	40058	40058	29967	7	30003	80106	200	80016	200	240048	40058	40060	1	1	80201	100	99	100	100	80000	80000	100	80015	15	0	0	2	80014	0	0	17	80000	16	0	14	0	1	1	1	5118	0	16	0	0	40049	80000	100	40048	40048	40053	40059	40061
80204	40058	300	1	1	2	0	0	0	14	1	0	0	1	40046	0	16	5	25	80100	100	80000	100	80006	500	1840277	0	40023	0	40047	40047	29971	7	29999	80106	200	80016	200	240048	40052	40052	1	1	80201	100	99	100	100	80000	80000	100	80015	16	36	0	1	80014	0	2	14	80002	16	36	14	2	1	1	1	5118	0	16	0	0	40057	80000	100	40048	40053	40049	40054	40060
80204	40052	300	1	0	0	0	0	0	14	1	0	0	1	40032	0	16	0	25	80100	100	80000	100	80007	500	1840275	0	40117	0	40050	40052	29970	7	30010	80106	200	80016	200	240048	40051	40053	1	1	80201	100	99	100	100	80000	80000	100	80015	16	36	0	1	80016	0	1	14	80000	14	0	14	0	1	1	1	5118	0	16	0	0	40056	80000	100	40053	40048	40048	40048	40048
80204	40057	300	1	1	1	0	0	0	20	1	0	0	1	40032	16	16	0	25	80100	100	80000	100	80006	500	1839862	0	40022	0	40058	40058	29976	7	30003	80106	200	80016	200	240048	40058	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	14	34	0	0	80016	0	0	17	80002	14	0	14	0	1	1	1	5118	0	16	0	0	40056	80000	100	40048	40060	40054	40049	40049
80204	40052	300	1	0	1	0	0	0	19	0	0	0	1	40044	0	16	0	25	80100	100	80000	100	80007	500	1839718	1	40026	0	40058	40058	29978	7	30012	80106	200	80016	200	240048	40058	40048	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	0	0	80014	0	0	14	80002	14	36	14	1	1	1	1	5118	0	16	0	0	40049	80000	100	40053	40048	40048	40049	40051
80204	40059	300	1	0	0	0	0	0	14	0	0	0	1	40032	16	16	5	25	80100	100	80000	100	80006	500	1840246	0	40034	0	40051	40047	29966	7	30004	80106	200	80016	200	240048	40047	40052	1	1	80201	100	99	100	100	80000	80000	100	80016	15	36	2	0	80016	0	2	14	80002	16	0	14	1	1	1	1	5118	0	16	0	0	40055	80000	100	40048	40053	40060	40054	40060
80204	40052	299	1	1	0	0	0	0	18	1	0	0	1	40032	0	16	0	25	80100	100	80000	100	80006	500	1840342	1	40028	0	40058	40060	29977	7	29999	80106	200	80016	200	240048	40048	40060	1	1	80201	100	99	100	100	80000	80000	100	80014	14	36	2	1	80016	0	1	18	80002	16	36	14	1	1	1	1	5118	0	16	0	0	40044	80000	100	40048	40048	40058	40053	40059

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	18	3	1	0	40035	0	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40052	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	34	0	5020	0	13	16	2	2	40039	80000	10	40051	40043	40050	40043	40050
80024	40042	300	0	0	48	0	1	0	40025	16	16	2	25	80010	10	80000	10	80000	50	1839760	40017	40042	40042	29977	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80000	2	34	0	5020	0	2	16	6	3	40039	80000	10	40274	40328	40043	40052	40193
80024	40042	302	0	0	729	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40049	40042	29977	3	30022	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80062	0	14	80062	2	34	0	5020	0	2	16	2	2	40039	80000	10	40043	40043	40043	40043	40052
80024	40042	300	0	0	12	3	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839424	40025	40213	40209	29980	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	34	0	5020	0	6	16	6	3	40039	80000	10	40043	40052	40043	40052	40043
80024	40051	299	0	0	39	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40052	40040	29977	3	30030	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	0	80002	0	0	0	5020	0	2	16	2	3	40039	80000	10	40052	40043	40052	40043	40043
80024	40042	299	0	0	87	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839856	40017	40042	40044	29977	3	30029	80010	20	80000	20	240000	40042	40049	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	34	0	5020	0	2	16	2	6	40039	80000	10	40043	40050	40043	40051	40043
80024	40042	300	0	1	42	91	0	0	40027	16	16	84	25	80010	10	80060	10	80000	50	1839424	40015	40043	40040	29977	3	30146	80010	20	80000	20	240000	40042	40050	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	0	80002	2	34	0	5020	0	2	24	2	2	40039	80000	10	40043	40051	40043	40051	40043
80024	40049	300	0	0	3	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40042	40042	29977	3	30030	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	2	80002	2	0	0	5020	0	2	16	2	2	40037	80000	10	40051	40043	40051	40043	40043
80024	40042	299	0	0	3	9	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	40017	40045	40045	29984	3	30022	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80002	0	0	80002	2	34	0	5020	0	2	16	2	6	40039	80000	10	40043	40043	40041	40052	40043
80024	40042	300	0	0	27	6	0	0	40036	16	16	0	25	80010	10	80000	10	80000	50	1839424	40017	40051	40042	29985	3	30022	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	34	80000	0	5	80002	2	34	0	5020	0	6	16	5	6	40039	80000	10	40043	40043	40043	40043	40051

STR (register, sxtw, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations