Firestorm: STR (register, uxtw, D) measurements

Code:

  str d0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	550	4	0	0	1	525	16	16	0	25	1000	1000	1000	22352	517	540	542	353	3	398	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	0	1000	0	0	1002	2	34	73	1	16	1	1	537	1000	541	543	541	541	541
1004	550	4	0	3	0	536	16	16	0	25	1000	1000	1000	22352	515	542	549	353	3	398	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	34	1002	0	2	1002	2	0	73	1	16	1	1	537	1000	541	543	543	543	543
1004	540	4	0	3	1	527	0	16	0	25	1000	1000	1000	22424	515	540	540	355	3	408	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	34	1002	0	0	1002	0	34	73	1	16	1	1	548	1000	543	543	543	543	541
1004	540	4	0	3	0	527	16	0	0	25	1000	1000	1000	22424	517	542	540	355	3	398	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	0	1002	0	5	1002	2	34	73	1	16	1	1	539	1000	543	550	551	551	541
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22424	517	542	542	355	3	398	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	1000	0	0	1002	2	34	73	1	16	1	1	539	1000	541	543	543	543	543
1004	542	4	0	3	0	535	16	16	0	25	1000	1000	1000	22352	515	542	551	355	3	398	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	0	1012	2	34	73	1	16	1	1	548	1000	543	543	543	543	541
1004	540	4	0	3	0	527	0	16	0	25	1000	1000	1000	22424	517	542	542	353	3	400	1000	1000	3000	551	540	1	1	1001	1000	1000	1000	34	1000	0	0	1002	0	34	73	1	16	1	1	537	1000	541	543	543	543	543
1004	542	4	0	0	1	527	16	0	0	25	1000	1000	1000	22352	517	542	542	353	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1000	0	2	1002	0	34	73	1	16	1	1	547	1000	543	543	543	543	541
1004	550	4	0	3	0	527	16	0	0	25	1000	1000	1000	22424	517	548	540	353	3	398	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	34	1002	0	8	1002	0	0	73	1	16	1	1	547	1000	543	543	543	541	541
1004	550	3	0	0	0	527	0	16	0	25	1000	1000	1000	22352	525	540	540	353	3	398	1000	1000	3000	542	540	1	1	1001	1000	1000	1000	34	1002	0	0	1002	0	34	73	1	16	1	1	546	1000	541	541	543	543	541

Count: 8

Code:

  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	24	0	1	40027	0	16	0	25	80100	100	80000	100	80007	500	1839378	1	40017	40042	40051	29961	7	29994	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	0	80000	0	2	80000	2	34	0	1	1	1	5118	0	16	0	0	40037	80000	100	40043	40041	40041	40043	40052
80204	40042	299	156	3	1	40027	16	16	0	25	80100	100	80000	100	80007	500	1839378	1	40015	40051	40040	29959	7	29994	80107	200	80016	200	240048	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	2	80000	0	34	0	1	1	1	5118	1	16	0	0	40037	80000	100	40041	40052	40041	40041	40041
80204	40042	300	120	3	1	40027	0	16	0	25	80100	100	80000	100	80007	500	1839455	1	40017	40040	40049	29969	7	29992	80106	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	0	80002	0	0	80000	2	0	0	1	1	1	5118	0	16	0	0	40039	80000	100	40051	40041	40041	40043	40041
80204	40042	299	0	3	1	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	40015	40040	40042	29961	7	30002	80106	200	80016	200	240048	40042	40051	2	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80000	0	2	80002	2	34	0	1	1	1	5118	0	16	0	0	40039	80000	100	40051	40041	40051	40043	40041
80204	40042	299	0	0	0	40025	16	0	0	25	80100	100	80000	100	80007	500	1839378	1	40015	40042	40042	29961	7	29994	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	0	80002	0	0	80002	2	34	0	1	1	1	5118	0	16	0	0	40037	80000	100	40041	40041	40043	40043	40043
80204	40042	300	108	0	1	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	1	40024	40042	40040	29959	7	29992	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	0	80000	0	2	80000	2	34	0	1	1	1	5118	0	16	0	0	40039	80000	100	40051	40041	40041	40041	40050
80204	40042	300	111	9	1	40027	16	0	0	25	80100	100	80000	100	80013	500	1839381	0	40015	40042	40042	29952	10	29982	80113	200	80022	200	240066	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	2	80000	2	0	0	2	2	2	5128	1	23	1	1	40039	80000	100	40043	40043	40043	40041	40052
80204	40042	300	441	6	1	40027	0	16	0	25	80100	100	80000	100	80012	500	1839381	1	40026	40042	40040	29950	10	29980	80112	200	80022	200	240066	40051	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	0	80000	0	0	80000	0	34	0	2	2	2	5128	1	23	1	1	40047	80000	100	40052	40043	40052	40043	40043
80204	40042	300	99	9	1	40027	16	16	0	25	80100	100	80000	100	80012	500	1839316	1	40017	40040	40042	29952	10	29990	80113	200	80022	200	240066	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	0	80002	0	2	80002	2	34	0	2	2	2	5128	1	23	1	1	40037	80000	100	40051	40041	40051	40043	40043
80204	40042	300	138	9	1	40035	16	16	0	25	80100	100	80000	100	80013	500	1839381	1	40015	40051	40050	29960	10	29982	80112	200	80022	200	240066	40049	40049	1	1	80201	100	99	100	100	80000	80000	100	80000	0	29	0	80002	0	2	80002	2	0	0	2	2	2	5128	1	23	1	1	40037	80000	100	40043	40043	40043	40052	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	40017	40042	40042	29977	3	30024	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80000	0	2	80002	2	42	5020	3	16	4	2	40039	1	0	80000	10	40041	40043	40043	40044	40041
80024	40043	299	0	0	0	3	0	40028	16	0	1	25	80010	10	80000	10	80000	50	1839352	40015	40040	40042	29978	3	30020	80010	20	80000	20	240000	40054	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	0	0	80002	2	42	5020	4	16	2	4	40051	0	0	80000	10	40043	40043	40041	40044	40044
80024	40043	299	0	0	0	3	1	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	40018	40043	40040	29977	3	30020	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80000	0	2	80000	0	0	5020	4	16	2	3	40037	0	0	80000	10	40043	40043	40041	40043	40043
80024	40042	299	0	0	0	3	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	40015	40040	40040	29977	3	30025	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80000	0	2	80012	2	0	5020	2	16	4	3	40039	0	0	80000	10	40043	40043	40044	40044	40044
80024	40043	300	0	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	40017	40042	40040	29977	3	30025	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80002	0	0	80000	2	42	5020	2	16	2	2	40039	0	0	80000	10	40041	40041	40043	40043	40043
80024	40040	300	0	0	0	3	1	40025	0	16	0	25	80010	10	80000	10	80000	50	1839448	40015	40040	40042	29975	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80000	1	2	80002	0	42	5020	4	16	2	2	40039	0	0	80000	10	40043	40041	40043	40043	40043
80024	40040	299	0	0	0	3	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	40015	40040	40042	29977	3	30027	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80002	0	0	80002	2	0	5020	2	16	2	3	40039	0	0	80000	10	40041	40041	40043	40043	40043
80024	40042	300	0	0	0	3	1	40027	16	16	0	25	80010	10	80000	10	80000	50	1840000	40017	40042	40040	29989	3	30020	80010	20	80000	20	240000	40122	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80002	0	2	80000	2	42	5020	2	16	2	4	40037	0	0	80000	10	40043	40041	40043	40043	40043
80024	40042	300	0	1	0	3	1	40028	16	16	1	25	80010	10	80000	10	80000	50	1839448	40017	40042	40040	29977	3	30024	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80002	0	0	80002	2	42	5020	2	16	2	2	40037	0	0	80000	10	40043	40041	40044	40041	40044
80024	40043	299	0	0	0	0	1	40028	16	16	1	25	80010	10	80000	10	80000	50	1839448	40017	40040	40042	29975	3	30022	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	80000	0	0	80002	2	42	5020	2	16	3	3	40037	0	0	80000	10	40043	40043	40043	40041	40041

STR (register, uxtw, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations