Firestorm: STR (register, uxtw, Q) measurements

Code:

  str q0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	3	1	527	16	16	1	25	1000	1000	1000	22448	517	542	542	355	3	400	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	555	544	543	544	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22472	517	542	543	356	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	540	1000	543	543	543	543	543
1004	542	3	33	3	1	528	16	16	1	25	1000	1000	1000	22448	517	542	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	543	543	543	543
1004	542	4	0	3	1	528	16	16	1	25	1000	1000	1000	22448	517	554	542	355	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	544	543	543	544	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22448	517	542	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	1	2	1002	2	42	73	2	16	2	2	540	1000	543	543	555	544	555
1004	542	4	0	3	1	528	16	16	1	25	1000	1000	1000	22448	517	542	542	355	3	400	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	544	543	544	543	544
1004	543	4	0	3	1	527	16	16	0	25	1000	1000	1000	22448	517	542	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	540	1000	543	543	543	543	543
1004	542	4	0	3	1	527	16	16	1	25	1000	1000	1000	22472	517	542	542	356	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	544	543	544	543	544
1004	543	4	0	3	1	528	16	16	1	25	1000	1000	1000	22448	517	542	542	367	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	544	543	543	544
1004	543	4	0	3	1	527	16	16	0	25	1000	1000	1000	22472	529	542	543	356	3	400	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	540	1000	543	543	543	543	543

Count: 8

Code:

  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]
  str q0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40050	300	0	3	1	0	40025	0	16	0	25	80100	100	80000	100	80007	500	1839455	1	40017	0	40052	40040	29959	7	29992	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80000	0	0	80002	2	34	0	1	1	1	5118	6	16	40048	0	80000	100	40043	40041	40043	40043	40041
80204	40042	300	33	3	1	0	40035	16	0	0	25	80100	100	80000	100	80007	500	1839378	1	40025	0	40212	40189	29961	7	29994	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80002	0	0	80002	2	34	0	1	1	1	5118	0	16	40037	0	80000	100	40043	40041	40043	40041	40043
80204	40042	300	0	0	1	0	40025	0	16	0	25	80100	100	80000	100	80007	500	1839378	1	40025	0	40040	40040	29961	7	29994	80106	200	80137	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80002	0	2	80002	2	36	0	1	1	1	5118	0	16	40039	0	80000	100	40043	40043	40041	40043	40050
80204	40040	300	36	0	0	0	40027	16	0	0	25	80100	100	80000	100	80006	500	1839378	1	40017	0	40042	40040	29971	7	29994	80107	200	80016	200	240048	40051	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80002	0	2	80002	2	36	0	1	1	1	5118	0	16	40037	0	80000	100	40043	40050	40043	40041	40043
80204	40040	300	24	3	0	0	40027	0	16	0	25	80100	100	80000	100	80006	500	1839378	1	40017	0	40042	40040	29959	7	30002	80107	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	2	80002	2	0	0	1	1	1	5118	0	16	40047	0	80000	100	40041	40043	40052	40043	40043
80204	40040	300	36	9	0	0	40027	0	16	0	25	80100	100	80000	100	80007	500	1839455	1	40017	0	40047	40040	29961	7	29992	80107	200	80016	200	240048	40049	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	0	2	80002	2	34	0	1	1	1	5118	0	16	40039	0	80000	100	40043	40041	40043	40050	40041
80204	40050	300	12	3	1	0	40036	16	16	0	25	80100	100	80000	100	80006	500	1839455	1	40015	0	40058	40042	29961	7	29992	80106	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80002	0	5	80000	2	0	0	1	1	1	5118	0	16	40039	0	80000	100	40041	40041	40041	40050	40043
80204	40042	300	45	3	1	0	40025	16	16	0	25	80100	100	80000	100	80006	500	1839455	1	40025	0	40042	40049	29959	7	29994	80107	200	80016	200	240048	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80002	0	2	80000	2	0	0	1	1	1	5118	0	16	40039	0	80000	100	40043	40043	40043	40043	40052
80204	40042	300	39	3	1	0	40027	16	0	0	25	80100	100	80000	100	80007	500	1839455	1	40017	0	40042	40040	29959	7	29992	80106	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	34	80000	0	2	80000	0	0	0	1	1	1	5118	0	16	40039	0	80000	100	40041	40052	40041	40052	40043
80204	40123	300	0	0	1	0	40025	0	16	2	25	80100	100	80000	100	80007	500	1839791	1	40017	0	40042	40040	29959	7	29994	80106	200	80016	200	240048	40042	40050	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	80002	2	34	0	1	1	1	5118	0	16	40039	0	80000	100	40043	40051	40041	40050	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	299	42	3	1	0	2	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40015	0	40040	40042	29977	3	30020	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	2	80002	0	42	0	5024	13	16	15	15	40039	80000	10	40043	40043	40041	40041	40043
80024	40040	300	258	3	0	0	2	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	40017	0	40042	40042	29978	3	30022	80010	20	80000	20	240000	40040	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	0	80002	0	42	0	5024	15	16	14	13	40040	80000	10	40041	40044	40043	40043	40044
80024	40040	300	72	7	0	0	2	40027	16	0	1	25	80010	10	80000	10	80000	50	1839448	1	40017	0	40040	40042	29977	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	2	80000	0	0	0	5024	17	16	15	17	40039	80000	10	40041	40043	40044	40041	40043
80024	40040	299	3	0	0	0	2	40039	16	0	0	25	80010	10	80000	10	80000	50	1840000	1	40017	0	40042	40042	29977	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80000	0	2	80002	0	42	0	5024	16	16	16	14	40040	80000	10	40044	40041	40043	40043	40043
80024	40042	300	99	0	1	0	2	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	1	40017	0	40042	40042	29977	3	30022	80010	20	80000	20	240000	40054	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	2	80000	2	0	0	5024	18	16	14	17	40037	80000	10	40041	40043	40041	40044	40043
80024	40042	300	111	0	1	0	2	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	40146	0	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	2	80002	0	42	0	5024	17	16	17	14	40037	80000	10	40043	40044	40041	40043	40041
80024	40040	299	72	0	0	0	2	40028	16	0	0	25	80010	10	80000	10	80000	50	1839448	1	40017	0	40042	40042	29978	3	30022	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	0	2	80000	0	0	0	5024	14	16	9	18	40040	80000	10	40044	40041	40043	40044	40041
80024	40043	300	357	0	0	0	2	40025	0	16	1	40	80010	10	80000	10	80000	50	1839448	1	40017	0	40040	40042	29989	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	0	80000	2	42	0	5024	13	16	14	16	40040	80000	10	40044	40043	40043	40044	40043
80024	40040	300	48	0	1	0	2	40025	0	0	0	25	80010	10	80000	10	80000	50	1840000	1	40015	0	40042	40042	29977	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80000	0	2	80002	2	42	0	5024	13	16	18	16	40039	80000	10	40041	40044	40043	40043	40043
80024	40042	300	87	0	1	0	2	40028	0	16	0	25	80010	10	80000	10	80000	50	1839448	1	40015	0	40042	40040	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80000	0	0	80000	0	0	0	5024	17	16	18	14	40039	80000	10	40043	40044	40044	40043	40044

STR (register, uxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations