Firestorm: STR (register, uxtw, S) measurements

Code:

  str s0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	543	4	1	1	1	1	0	19	0	0	1	539	16	16	1	25	1000	1000	1000	23004	0	526	554	554	376	3	410	1000	1000	3000	554	553	1	1	1001	1000	1000	1016	14	44	0	0	1016	0	1	19	1002	16	0	14	0	73	3	16	3	3	537	1000	543	543	543	543	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	0	25	1000	1000	1000	22448	0	517	542	542	367	3	400	1000	1000	3000	554	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	2	16	1002	16	44	14	0	73	3	16	3	3	551	1000	553	565	555	555	555
1004	554	4	1	1	1	0	3	21	0	0	1	537	16	16	1	25	1000	1000	1000	23004	0	538	554	547	368	3	409	1000	1000	3000	555	553	1	1	1001	1000	1000	1014	14	44	0	1	1016	0	0	18	1002	16	44	14	2	73	3	16	3	3	551	1000	553	555	555	548	555
1004	554	4	1	0	1	1	0	19	0	0	1	539	16	16	2	25	1000	1000	1000	22884	0	529	554	563	367	3	412	1000	1000	3000	554	552	1	1	1001	1000	1000	1016	14	44	0	0	1016	0	0	17	1002	16	44	14	0	73	3	16	2	3	551	1000	555	555	553	553	549
1004	564	4	1	1	0	0	0	19	0	0	1	539	16	16	1	25	1000	1000	1000	23028	0	529	552	554	365	3	412	1000	1000	3000	552	554	1	1	1001	1000	1000	1014	14	44	0	0	1016	0	0	16	1002	16	44	14	0	73	3	16	3	3	551	1000	553	553	564	555	556
1004	554	4	1	0	1	0	0	18	0	0	1	539	16	16	1	25	1000	1000	1000	22692	0	526	554	554	376	3	410	1000	1000	3000	554	553	1	1	1001	1000	1000	1014	14	0	0	0	1014	0	0	16	1002	16	44	14	1	73	3	16	3	3	549	1000	555	555	553	553	553
1004	563	4	1	1	1	0	0	17	0	0	1	538	16	16	5	25	1000	1000	1000	22908	0	529	554	548	367	3	412	1000	1000	3000	554	552	1	1	1001	1000	1000	1014	16	44	0	1	1016	0	2	17	1000	16	42	14	1	73	2	16	3	3	551	1000	555	555	553	552	553
1004	563	4	1	0	0	0	0	17	0	0	1	537	16	16	6	25	1000	1000	1000	22933	0	522	552	554	367	3	412	1000	1000	3000	553	554	1	1	1001	1000	1000	1015	15	44	1	0	1016	0	2	14	1002	16	44	14	0	73	3	16	3	3	551	1000	555	553	552	564	564
1004	554	4	1	0	0	1	0	19	1	0	1	537	16	16	6	25	1000	1000	1000	22933	0	529	552	554	367	3	412	1000	1000	3000	554	554	1	1	1001	1000	1000	1015	14	44	0	2	1014	0	0	18	1002	16	44	14	0	73	3	16	3	3	548	1000	553	553	564	555	556
1004	554	4	1	0	0	1	0	19	0	0	1	539	16	15	0	25	1000	1000	1000	23004	0	538	554	551	367	3	406	1000	1000	3000	554	552	1	1	1001	1000	1000	1015	14	43	0	1	1016	0	0	16	1000	16	44	14	1	73	3	16	3	3	549	1000	555	548	553	564	555

Count: 8

Code:

  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]
  str s0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	3	1	0	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839378	0	40018	0	40042	40042	29962	7	29994	80106	200	80016	200	240048	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80000	2	0	0	1	1	1	5118	1	16	0	1	40043	80000	100	40043	40043	40044	40041	40044
80204	40043	300	0	0	0	3	0	0	0	40027	0	16	0	25	80100	100	80000	100	80006	500	1839474	1	40017	3	40042	40042	29973	7	29994	80106	200	80016	200	240048	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	5	80002	2	42	0	1	1	1	5118	0	16	0	0	40041	80000	100	40044	40044	40043	40041	40043
80204	40040	300	0	0	0	0	0	0	0	40025	16	0	0	25	80100	100	80000	100	80006	500	1839474	1	40017	0	40042	40040	29961	7	29992	80106	200	80016	200	240048	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80000	0	0	5	80002	2	42	0	1	1	1	5118	0	16	0	0	40041	80000	100	40044	40041	40043	40043	40043
80204	40042	299	0	0	0	3	1	0	0	40027	16	0	0	25	80100	100	80000	100	80006	500	1839503	1	40015	0	40040	40042	29952	10	29980	80112	200	80022	200	240066	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	1	0	0	80000	2	0	0	2	2	2	5128	1	23	1	1	40039	80000	100	40043	40180	40322	40195	40184
80204	40040	299	0	0	6	3	0	0	0	40027	0	0	0	25	80100	100	80000	100	80012	500	1839412	1	40015	0	40042	40042	29952	10	29982	80112	200	80022	200	240066	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	6	80002	2	42	0	2	2	2	5128	1	23	1	1	40041	80000	100	40041	40043	40044	40043	40044
80204	40042	300	0	0	0	3	0	0	0	40028	16	16	0	25	80100	100	80000	100	80013	500	1839412	1	40017	0	40042	40042	29953	10	29982	80113	200	80022	200	240066	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	3	0	5	80002	2	42	0	2	2	2	5128	1	23	1	1	40040	80000	100	40044	40041	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	0	40027	16	0	1	25	80100	100	80000	100	80012	500	1839429	1	40015	0	40043	40043	29952	10	29982	80113	200	80022	200	240066	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	0	80002	2	42	0	2	2	2	5128	1	23	1	1	40037	80000	100	40123	40041	40044	40043	40046
80204	40042	300	0	0	0	3	1	0	0	40027	16	16	0	25	80100	100	80000	100	80012	500	1839412	1	40017	0	40042	40122	29964	10	29980	80112	200	80022	200	240066	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	2	2	2	5128	1	23	1	1	40037	80000	100	40041	40043	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	0	40027	16	0	0	25	80100	100	80000	100	80012	500	1839412	0	40017	0	40042	40042	29952	10	29980	80112	200	80022	200	240066	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80000	0	0	2	80002	2	0	0	2	2	2	5128	1	23	1	2	40037	80000	100	40043	40043	40053	40041	40043
80204	40042	300	0	0	0	7	0	0	0	40028	0	16	0	25	80100	100	80000	100	80012	500	1839412	1	40015	0	40040	40043	29952	10	29983	80112	200	80022	200	240066	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80000	0	0	2	80002	0	42	0	2	2	2	5128	1	23	1	2	40039	80000	100	40041	40044	40041	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40015	40043	40043	29975	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	0	0	0	80002	2	42	0	0	5020	5	16	0	0	4	3	40040	0	80000	10	40043	40044	40043	40043	40043
80024	40054	300	0	0	0	0	3	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839448	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	0	2	80000	2	0	0	0	5020	3	16	0	0	3	4	40039	0	80000	10	40043	40043	40041	40041	40044
80024	40040	300	0	0	0	0	3	1	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839352	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	0	2	80002	0	0	0	0	5020	3	16	0	0	4	4	40040	0	80000	10	40044	40053	40041	40041	40043
80024	40043	299	0	0	0	0	3	0	0	40027	16	16	2	25	80010	10	80000	10	80000	50	1839448	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	0	0	0	80000	2	0	0	0	5020	3	16	0	0	4	4	40039	0	80000	10	40043	40043	40043	40041	40043
80024	40042	300	0	0	0	0	0	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1840000	0	40015	40042	40042	29989	3	30022	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80000	0	0	2	80000	2	42	0	0	5020	4	16	0	0	4	4	40039	0	80000	10	40041	40041	40043	40043	40043
80024	40054	300	0	0	0	0	3	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40015	40042	40042	29975	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80000	0	0	0	80000	2	0	0	0	5020	4	16	0	0	3	4	40039	0	80000	10	40043	40041	40041	40043	40043
80024	40042	300	0	0	0	0	3	1	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839448	0	40015	40042	40040	29977	3	30020	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	0	0	80002	0	42	0	0	5020	4	16	0	0	4	4	40039	0	80000	10	40043	40041	40041	40041	40041
80024	40054	300	0	0	0	0	3	0	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839352	1	40015	40042	40040	29975	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80000	0	0	0	80000	2	0	0	0	5020	4	16	0	0	4	4	40037	0	80000	10	40041	40043	40041	40041	40043
80024	40040	300	0	0	0	0	0	0	0	40028	0	0	1	25	80010	10	80000	10	80000	50	1839472	0	40018	40042	40042	29975	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80000	1	0	0	80002	0	42	0	0	5020	4	16	0	0	3	4	40039	0	80000	10	40043	40055	40043	40041	40043
80024	40040	300	0	0	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	40040	40042	29987	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	42	0	0	80002	0	0	2	80002	2	42	0	0	5020	4	16	0	0	3	3	40037	0	80000	10	40041	40043	40044	40043	40044

STR (register, uxtw, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations