Firestorm: STR (signed offset, D) measurements

Code:

  str d0, [x6, #0x10]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	559	4	0	1	1	1	0	14	0	3	538	16	16	5	25	1000	1000	1000	23244	1	522	547	559	364	3	405	1000	1000	2000	558	552	1	1	1001	1000	1000	1014	14	0	0	0	1014	0	0	18	1002	14	0	14	0	77	5	16	5	5	557	1000	554	553	551	562	549
1004	559	4	1	1	1	0	0	21	1	3	537	16	15	5	25	1000	1000	1000	23268	1	533	552	559	365	3	405	1000	1000	2000	552	547	1	1	1001	1000	1000	1014	15	0	0	2	1014	0	1	19	1002	16	36	14	1	77	5	16	5	5	555	1000	560	559	559	548	554
1004	552	4	1	1	0	0	0	15	0	3	543	14	16	2	25	1000	1000	1000	22692	1	526	558	552	360	3	405	1000	1000	2000	547	558	1	1	1001	1000	1000	1015	15	36	1	0	1014	0	0	16	1002	16	36	14	2	77	5	16	5	5	544	1000	560	560	553	552	548
1004	547	4	1	1	0	1	0	18	0	3	537	16	15	5	25	1000	1000	1000	23268	1	522	547	547	365	3	416	1000	1000	2000	552	559	1	1	1001	1000	1000	1014	16	0	0	1	1016	0	1	15	1002	16	35	14	1	77	5	16	5	5	550	1000	559	548	554	553	548
1004	547	4	0	1	1	1	0	18	0	3	536	0	0	0	25	1000	1000	1000	22956	1	522	559	552	360	3	410	1000	1000	2000	560	559	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	1	20	1002	16	0	14	1	77	5	16	5	5	544	1000	548	553	554	552	551
1004	560	4	1	1	1	0	0	18	0	3	536	16	15	5	25	1000	1000	1000	23220	1	534	547	558	365	3	405	1000	1000	2000	552	561	1	1	1001	1000	1000	1016	15	36	0	1	1016	0	0	20	1000	16	36	14	1	77	5	16	5	5	549	1000	560	548	559	553	553
1004	552	4	1	1	1	0	0	19	1	3	543	14	0	9	25	1000	1000	1000	23340	1	522	558	552	370	3	409	1000	1000	2000	548	547	1	1	1001	1000	1000	1015	15	0	0	1	1016	0	0	22	1000	16	0	14	2	77	5	16	5	5	548	1000	548	553	551	548	559
1004	559	4	1	1	1	1	0	14	0	3	544	16	16	2	25	1000	1000	1000	22692	1	522	559	549	360	3	419	1000	1000	2000	547	551	1	1	1001	1000	1000	1014	14	36	0	0	1014	1	0	17	1002	16	0	14	0	77	5	16	5	5	544	1000	553	551	562	558	560
1004	559	4	1	1	1	1	6	14	0	3	544	16	16	8	25	1000	1000	1000	22788	1	523	559	550	371	3	405	1000	1000	2000	547	552	1	1	1001	1000	1000	1015	14	36	0	1	1016	0	1	18	1000	16	36	14	0	77	5	16	5	5	549	1000	548	548	553	553	548
1004	547	4	1	1	1	1	0	14	0	3	542	0	16	0	25	1000	1000	1000	22908	1	534	552	547	365	3	417	1000	1000	2000	552	560	1	1	1001	1000	1000	1016	15	36	0	1	1014	0	0	20	1002	16	0	14	0	77	5	16	5	5	545	1000	553	551	562	560	548

Count: 8

Code:

  str d0, [x6, #0x10]
  str d0, [x6, #0x10]
  str d0, [x6, #0x10]
  str d0, [x6, #0x10]
  str d0, [x6, #0x10]
  str d0, [x6, #0x10]
  str d0, [x6, #0x10]
  str d0, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	300	0	0	0	0	0	0	0	3	0	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	1	40015	40042	40040	29956	3	30000	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	6	80002	2	0	5110	1	16	1	1	40037	0	80000	100	40043	40043	40044	40044	40053
80204	40042	299	0	0	0	0	0	0	0	0	1	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	1	40017	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	11	80000	0	0	5110	1	16	1	1	40037	0	80000	100	40041	40041	40041	40044	40043
80204	40040	300	0	0	0	0	0	0	0	3	0	0	0	40039	16	16	0	25	80100	100	80000	100	80000	500	1839448	0	40015	40042	40040	29953	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	12	80000	2	0	5110	1	16	1	1	40037	0	80000	100	40043	40043	40043	40055	40041
80204	40042	300	0	0	0	0	0	0	0	3	0	0	0	40028	16	16	1	25	80100	100	80000	100	80432	500	1839448	1	40017	40042	40043	29955	3	29998	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80000	4	4	116	80002	0	42	5110	1	16	1	1	40040	0	80000	100	40055	40043	40043	40043	40043
80204	40040	299	0	0	0	0	0	0	675	7	0	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839472	0	40018	40040	40042	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	0	0	131	80000	2	42	5110	1	16	1	1	40051	0	80000	100	40043	40043	40052	40043	40043
80204	40042	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839472	1	40015	40040	40040	29953	3	29998	80100	200	80000	200	160000	40054	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	7	0	3	80002	2	42	5110	1	16	1	1	40039	0	80000	100	40041	40043	40041	40043	40044
80204	40054	300	0	0	0	0	0	0	0	0	1	0	0	40025	0	0	0	25	80100	100	80000	100	80000	500	1839472	1	40015	40043	40042	29965	3	30000	80100	200	80000	200	160000	40043	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	0	0	5	80000	2	0	5110	1	16	1	1	40039	0	80000	100	40041	40041	40043	40043	40043
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40036	16	0	0	25	80100	100	80000	100	80000	500	1839448	1	40015	40042	40043	29955	3	30001	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80000	0	0	5	80000	2	42	5110	1	16	1	1	40039	0	80000	100	40043	40043	40055	40041	40043
80204	40042	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839496	1	40017	40042	40042	29953	3	30012	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	42	0	80002	0	0	8	80000	0	42	5110	1	16	1	1	40037	0	80000	100	40043	40043	40041	40043	40044
80204	40042	300	0	0	0	0	0	0	6	0	0	0	0	40025	16	16	1	25	80100	100	80000	100	80000	500	1839352	1	40015	40042	40042	29953	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80000	0	0	3	80002	2	44	5110	1	16	1	1	40039	0	80000	100	40043	40043	40044	40044	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	299	0	0	0	0	12	3	0	0	40028	16	16	1	25	80010	10	80000	10	80000	50	1839472	0	40017	40043	40043	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	5	80002	2	42	0	0	5020	9	16	0	4	6	40039	0	80000	10	40043	40043	40044	40043	40041
80024	40043	300	0	0	0	0	6	3	1	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	0	40018	40042	40042	29978	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	2	80002	2	42	0	0	5020	8	16	0	6	4	40040	4	80000	10	40043	40043	40043	40043	40043
80024	40042	300	0	0	0	0	0	3	1	0	40028	16	16	1	25	80010	10	80000	10	80000	50	1839472	0	40491	40040	40043	29977	3	30023	80010	20	80000	20	160000	40040	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	29	0	80000	0	0	80002	2	42	0	0	5020	6	16	0	6	4	40037	0	80000	10	40043	40043	40043	40043	40043
80024	40042	300	0	0	0	0	0	3	1	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	0	40015	40042	40042	29989	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	80000	2	42	0	0	5020	6	16	0	4	6	40037	0	80000	10	40041	40043	40041	40043	40043
80024	40040	300	0	0	0	0	0	3	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839472	0	40017	40042	40043	29977	3	30020	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	2	80000	2	42	0	0	5020	5	16	0	8	6	40039	0	80000	10	40043	40041	40043	40043	40043
80024	40040	300	0	0	0	0	6	3	1	0	40028	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40018	40040	40043	29977	3	30022	80010	20	80000	20	160000	40043	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	2	80000	0	42	0	0	5020	5	16	0	6	7	40040	0	80000	10	40044	40044	40043	40043	40044
80024	40040	300	0	0	0	0	0	3	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839448	0	40017	40042	40042	29977	3	30034	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	2	80002	2	42	0	0	5020	7	16	0	5	6	40039	0	80000	10	40043	40044	40044	40041	40041
80024	40042	300	0	0	0	0	24	3	1	0	40027	16	16	28	25	80010	10	80000	10	80000	50	1839448	0	40017	40043	40042	29975	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	80002	2	42	0	0	5020	4	16	0	7	5	40039	0	80000	10	40041	40044	40044	40041	40044
80024	40042	299	0	0	0	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	40018	40042	40042	29978	3	30022	80010	20	80000	20	160000	40052	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	2	80002	0	0	0	0	5020	6	16	0	6	7	40172	0	80000	10	40041	40053	40043	40043	40043
80024	40042	300	0	0	0	0	12	3	0	0	40027	16	16	0	55	80070	10	80000	10	80000	50	1839448	0	40019	40042	40318	30072	3	30020	80010	20	80000	20	160000	40182	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	2	80000	2	42	0	0	5020	5	16	0	4	6	40040	0	80000	10	40043	40055	40043	40041	40043

STR (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations