Firestorm: STR (signed offset, Q) measurements

Code:

  str q0, [x6, #0x10]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	3	1	528	16	16	5	25	1000	1000	1000	22472	1	518	543	543	355	3	400	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	544	544	543	543	543
1004	542	4	0	3	0	528	16	16	1	25	1000	1000	1000	22472	1	518	542	542	355	3	401	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	555	543
1004	542	4	0	3	0	527	16	16	1	25	1000	1000	1000	22448	1	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22472	1	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	527	16	16	5	25	1000	1000	1000	22448	1	517	543	543	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	555	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22448	1	517	542	542	356	3	400	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	551	1000	543	555	543	543	543
1004	542	4	0	3	0	527	16	16	1	25	1000	1000	1000	22448	1	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	544	544
1004	542	4	0	3	0	527	16	16	1	25	1000	1000	1000	22448	1	517	542	542	355	3	401	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22448	1	517	542	542	355	3	400	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	554	4	0	3	0	527	16	16	0	25	1000	1000	1000	22448	1	517	542	542	355	3	400	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543

Count: 8

Code:

  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40050	300	0	0	0	0	0	9	1	0	40036	16	0	0	25	80100	100	80000	100	80000	500	1839424	0	40015	40042	40040	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80002	0	2	80002	2	34	5112	1	16	1	2	2	40037	80000	100	40043	40043	40043	40043	40052
80204	40042	299	0	0	0	0	0	3	1	0	40035	16	16	0	25	80100	100	80000	100	80000	500	1850602	0	40026	40042	40042	30324	3	30000	80100	200	80000	200	160000	40042	40464	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80002	0	2	80002	2	34	5112	1	16	1	1	2	40037	80000	100	40043	40043	40043	40050	40043
80204	40042	300	0	0	0	0	0	6	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839784	0	40017	40050	40042	29962	3	30000	80100	200	80000	200	160000	40040	40049	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80000	0	2	80002	2	34	5112	1	16	1	1	2	40039	80000	100	40043	40604	40043	40051	40043
80204	40040	300	0	0	0	0	0	6	1	0	40027	16	16	3	25	80100	100	80000	100	80000	500	1839424	0	40017	40040	40042	29953	3	30008	80100	200	80000	200	160000	40321	40182	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80062	0	2	80002	2	34	5112	1	16	1	1	2	40048	80000	100	40043	40043	40052	40043	40043
80204	40042	300	0	0	0	0	0	3	1	0	40036	0	16	0	25	80100	100	80000	100	80000	500	1839352	0	40017	40042	40051	29964	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80002	0	2	80002	2	34	5112	1	16	1	1	2	40039	80000	100	40043	40043	40043	40050	40043
80204	40042	300	0	0	0	0	0	9	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	40015	40042	40040	29955	3	30009	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	0	2	80002	2	34	5112	1	16	1	1	2	40039	80000	100	40043	40051	40043	40043	40598
80204	40051	300	0	0	0	0	0	3	0	0	40034	16	16	0	25	80100	100	80000	100	80000	500	1839424	2	40017	40042	40051	29955	3	29998	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80000	0	2	80002	0	34	5112	1	16	1	1	2	40039	80000	100	40041	40041	40041	40041	40041
80204	40040	300	0	0	0	0	0	3	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839832	0	40017	40049	40049	29953	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	0	80002	0	2	80002	2	34	5112	1	16	1	1	2	40039	80000	100	40051	40041	40051	40041	40041
80204	40042	300	0	0	0	0	0	3	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839352	0	40017	40040	40050	29963	3	30000	80100	200	80000	200	160000	40049	40042	1	1	80201	100	99	100	100	80000	80000	100	80062	34	0	80002	1	0	80002	0	0	5112	1	16	1	3	2	40039	80000	100	40043	40041	40043	40043	40043
80204	40040	300	0	0	0	0	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839856	0	40017	40042	40050	29964	3	29998	80100	200	80000	200	160000	40051	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80002	3	2	80002	2	34	5112	1	16	1	1	2	40039	80000	100	40043	40041	40043	40050	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40058	299	1	0	1	1	0	0	0	19	1	0	0	1	40043	16	16	84	25	80010	10	80000	10	80000	50	1839692	0	40035	40052	40058	29994	3	30038	80010	20	80000	20	160000	40052	40052	1	1	80021	10	9	10	10	80000	80000	10	80014	15	36	0	1	80016	0	0	18	80002	16	36	14	0	5020	7	16	0	10	6	40050	0	80000	10	40061	40060	40051	40059	40060
80024	40052	299	1	1	1	0	0	0	0	17	1	0	0	1	40032	16	0	2	25	80010	10	80000	10	80000	50	1839812	0	40033	40058	40050	29985	3	30032	80010	20	80000	20	160000	40060	40051	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	1	80016	1	2	20	80000	16	36	14	0	5020	6	16	0	8	12	40045	0	80000	10	40059	40048	40060	40052	40053
80024	40060	300	1	1	1	0	0	0	0	19	1	0	0	1	40044	0	16	8	25	80010	10	80000	10	80000	50	1840199	0	40027	40059	40059	29993	3	30031	80010	20	80000	20	160000	40059	40061	1	1	80021	10	9	10	10	80000	80000	10	80015	14	36	0	1	80014	1	0	19	80000	14	0	14	0	5020	6	16	0	6	10	40044	0	80000	10	40052	40060	40053	40059	40051
80024	40047	300	1	0	0	1	0	0	0	20	0	0	0	1	40032	15	16	1	25	80010	10	80000	10	80000	50	1840316	0	40027	40057	40047	29982	3	30033	80010	20	80000	20	160000	40047	40047	1	1	80021	10	9	10	10	80000	80000	10	80016	15	34	0	0	80016	0	2	18	80002	16	36	14	1	5020	6	16	0	7	10	40055	0	80000	10	40048	40060	40053	40059	40061
80024	40058	299	1	0	1	0	0	0	0	17	1	0	0	1	40035	0	16	0	25	80010	10	80000	10	80000	50	1840340	0	40027	40057	40047	29996	3	30032	80010	20	80000	20	160000	40047	40047	1	1	80021	10	9	10	10	80000	80000	10	80015	14	36	0	1	80016	0	1	14	80002	16	36	14	0	5020	10	16	0	10	6	40055	0	80000	10	40060	40053	40048	40053	40059
80024	40050	300	1	1	0	1	0	0	0	14	1	0	0	1	40035	16	16	299	25	80010	10	80000	10	80000	50	1840316	0	40027	40057	40060	29982	3	30027	80010	20	80000	20	160000	40058	40047	1	1	80021	10	9	10	10	80000	80000	10	80014	16	0	2	0	80016	0	0	18	80002	16	0	14	1	5020	10	16	0	10	6	40054	0	80000	10	40054	40059	40052	40060	40061
80024	40059	300	1	1	1	0	0	0	0	18	1	0	0	1	40045	0	16	6	25	80010	10	80000	10	80216	50	1840221	0	40156	40205	40061	29993	3	30032	80010	20	80000	20	160000	40057	40060	1	1	80021	10	9	10	10	80000	80000	10	80015	14	36	0	1	80014	0	2	18	80002	14	36	14	1	5020	6	16	0	6	10	40055	0	80000	10	40048	40048	40053	40048	40061
80024	40047	300	1	1	1	1	0	0	0	19	0	0	0	1	40032	0	16	5	25	80010	10	80000	10	80000	50	1839692	0	40033	40053	40058	29987	3	30038	80010	20	80000	20	160000	40047	40058	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	1	80016	0	0	20	80000	16	36	14	0	5020	6	16	0	10	6	40044	0	80000	10	40052	40059	40048	40060	40048
80024	40059	300	1	0	0	1	0	0	0	14	1	0	0	1	40043	0	16	2	25	80010	10	80000	10	80000	50	1840340	0	40022	40057	40060	29996	3	30027	80010	20	80000	20	160000	40059	40049	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	1	80014	0	0	14	80002	16	36	14	1	5020	10	16	0	10	6	40049	0	80000	10	40048	40059	40048	40048	40059
80024	40059	300	1	0	1	0	0	0	0	19	0	0	0	1	40032	16	16	9	25	80010	10	80000	10	80000	50	1839884	0	40033	40060	40052	29986	3	30039	80010	20	80000	20	160000	40050	40047	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	2	80016	1	0	20	80002	16	36	14	0	5020	7	16	0	6	10	40044	0	80000	10	40053	40048	40060	40051	40053

STR (signed offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations