Firestorm: STR (signed offset, S) measurements

Code:

  str s0, [x6, #0x10]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	564	4	1	1	0	0	0	18	1	0	1	539	16	16	2	25	1000	1000	1000	23028	0	529	554	563	367	3	412	1000	1000	2000	563	554	1	1	1001	1000	1000	1015	14	44	0	1	1016	1	16	1002	16	43	14	1	73	1	16	1	1	551	1000	555	555	554	553	554
1004	554	4	1	1	1	1	0	18	1	0	1	537	16	16	0	25	1000	1000	1000	23438	1	529	552	554	367	3	421	1000	1000	2000	563	554	1	1	1001	1000	1000	1015	15	44	0	1	1016	1	17	1002	16	43	14	1	73	1	16	1	1	551	1000	555	555	555	554	555
1004	554	4	1	0	1	0	0	19	0	0	1	539	16	16	1	25	1000	1000	1000	22884	0	527	554	554	364	3	412	1000	1000	2000	554	552	1	1	1001	1000	1000	1016	15	44	0	2	1016	1	16	1002	16	44	14	1	73	1	16	1	1	549	1000	553	553	553	564	553
1004	552	4	1	1	1	1	0	19	0	0	1	539	16	16	1	25	1000	1000	1000	22884	1	529	553	554	367	3	410	1000	1000	2000	552	554	1	1	1001	1000	1000	1015	15	44	0	0	1016	2	16	1002	16	44	14	0	73	1	16	1	1	551	1000	555	555	554	552	554
1004	554	4	1	1	1	1	0	17	0	0	1	539	16	16	2	25	1000	1000	1000	22884	0	526	555	554	365	3	412	1000	1000	2000	554	551	1	1	1001	1000	1000	1016	14	44	0	2	1016	1	19	1002	16	43	14	0	73	1	16	1	1	549	1000	552	553	564	555	556
1004	554	4	1	1	1	1	0	18	1	0	1	548	16	16	1	25	1000	1000	1000	22908	1	529	553	564	367	3	410	1000	1000	2000	552	554	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	16	1002	16	44	14	1	73	1	16	1	1	551	1000	555	556	555	555	555
1004	554	4	1	0	1	0	0	18	1	0	1	549	16	16	5	25	1000	1000	1000	22956	0	528	554	552	367	3	410	1000	1000	2000	552	554	1	1	1001	1000	1000	1014	15	44	0	0	1016	0	18	1002	16	44	14	1	73	1	16	1	1	551	1000	555	555	555	553	555
1004	554	4	1	0	0	1	3	18	1	0	1	539	15	16	1	25	1000	1000	1000	22908	1	529	554	563	367	3	410	1000	1000	2000	552	554	1	1	1001	1000	1000	1015	15	44	0	0	1016	0	17	1002	16	44	14	2	73	1	16	1	1	551	1000	554	552	553	564	553
1004	552	4	1	0	1	1	0	18	1	0	1	539	15	16	2	25	1000	1000	1000	22884	0	527	554	554	364	3	412	1000	1000	2000	554	553	1	1	1001	1000	1000	1014	15	44	0	0	1016	1	18	1002	16	44	14	2	73	1	16	1	1	551	1000	555	555	553	553	553
1004	553	4	1	1	0	1	0	105	0	0	1	540	16	16	2	25	1000	1000	1000	23438	0	539	552	555	367	3	421	1000	1000	2000	552	554	1	1	1001	1000	1000	1014	16	44	0	1	1016	0	16	1002	16	44	14	0	73	1	16	1	1	548	1000	553	552	553	564	564

Count: 8

Code:

  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	299	1	0	0	1	0	17	1	0	1	40039	0	16	2	25	80100	100	80000	124	80000	500	1839956	0	40029	40047	40053	29964	3	30005	80100	200	80000	200	160000	40064	40052	1	1	80201	100	99	100	100	80000	80000	100	80015	14	44	0	2	80016	0	0	16	80002	16	44	14	1	5110	1	16	1	1	40049	80000	100	40065	40048	40053	40055	40048
80204	40054	300	1	0	1	1	0	14	0	0	1	40037	0	16	5	25	80100	100	80000	100	80000	500	1839692	0	40027	40054	40054	29967	3	30021	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	44	0	1	80014	0	0	14	80000	14	44	14	1	5110	1	16	1	1	40048	80000	100	40064	40055	40064	40055	40056
80204	40047	300	1	0	1	1	6	18	1	0	1	40049	0	16	0	25	80100	100	80000	100	80000	500	1839692	0	40028	40054	40054	29967	3	30010	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80016	15	0	0	2	80014	0	1	20	80000	16	44	14	2	5110	1	16	1	1	40051	80000	100	40055	40048	40055	40048	40055
80204	40048	299	1	0	1	1	0	14	0	0	1	40049	16	16	0	25	80100	100	80000	100	80000	500	1839692	0	40029	40052	40053	29960	3	30012	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	15	44	0	2	80014	0	0	14	80002	16	44	14	1	5110	1	16	1	1	40051	80000	100	40048	40048	40048	40048	40053
80204	40054	300	1	0	0	1	0	19	1	0	1	40039	16	16	2	25	80100	100	80000	100	80000	500	1840004	0	40029	40051	40047	29960	3	30005	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	44	0	1	80016	0	2	18	80000	16	44	14	0	5110	1	16	1	1	40051	80000	100	40048	40064	40048	40053	40048
80204	40064	300	1	1	0	1	0	18	0	0	1	40032	0	0	1	25	80100	100	80000	100	80000	500	1840004	0	40029	40047	40047	29966	3	30005	80100	200	80000	200	160000	40052	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	14	0	0	0	80016	0	0	19	80002	16	44	14	0	5110	1	16	1	1	40051	80000	100	40055	40048	40055	40048	40048
80204	40052	300	1	0	1	0	0	14	0	0	1	40038	16	16	2	25	80100	100	80000	100	80000	500	1839692	0	40029	40064	40052	29960	3	30012	80100	200	80000	200	160000	40052	40047	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	0	0	80014	0	0	33	80000	16	44	14	1	5110	1	16	1	1	40051	80000	100	40052	40055	40053	40055	40053
80204	40054	300	1	1	0	0	0	19	0	0	1	40037	16	16	4	25	80100	100	80000	100	80000	500	1840438	0	40030	40047	40047	29967	3	30005	80100	200	80000	200	160000	40054	40064	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	0	0	80016	0	2	16	80000	16	44	14	0	5110	1	16	1	1	40051	80000	100	40048	40056	40054	40048	40053
80204	40047	300	1	0	0	0	0	18	1	0	1	40032	0	16	2	25	80100	100	80000	100	80000	500	1840028	0	40022	40053	40047	29967	3	30005	80100	200	80000	200	160000	40054	40054	1	1	80201	100	99	100	100	80000	80000	100	80014	15	0	0	2	80014	0	0	14	80000	16	44	14	0	5110	1	16	1	1	40060	80000	100	40048	40055	40054	40055	40053
80204	40054	300	1	0	1	1	0	19	1	0	1	40039	15	0	1	25	80100	100	80000	100	80000	500	1840004	0	40022	40047	40047	29967	3	30005	80100	200	80000	200	160000	40054	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	15	44	0	0	80014	0	1	20	80000	2	44	14	0	5110	1	16	1	1	40050	80000	100	40052	40055	40052	40055	40064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40050	300	0	0	0	0	0	0	108	19	1	0	0	0	40038	16	0	4	25	80010	10	80000	10	80000	50	1840220	1	40022	40049	40057	29975	3	30032	80010	20	80000	20	160000	40058	40050	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	1	80016	1	0	20	80002	16	0	14	1	0	5020	3	16	3	3	40049	80000	10	40053	40059	40048	40060	40051
80024	40059	300	1	1	0	1	0	0	36	18	1	0	0	0	40044	16	14	0	25	80010	10	80000	10	80000	50	1840292	1	40036	40053	40052	29975	3	30022	80010	20	80000	20	160000	40049	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	8	80000	2	34	0	0	0	5020	5	16	4	3	40050	80000	10	40048	40059	40052	40048	40061
80024	40059	300	1	0	0	0	0	0	300	3	1	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	1	40022	40061	40058	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	0	0	5020	4	16	4	2	40044	80000	10	40058	40048	40059	40048	40048
80024	40053	300	1	0	0	0	0	0	24	3	1	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1840193	1	40017	40050	40047	29982	3	30032	80010	20	80000	20	160000	40057	40047	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	0	80016	0	0	17	80002	16	0	14	1	0	5020	4	16	5	5	40039	80000	10	40052	40043	40052	40043	40043
80024	40042	300	0	0	0	0	0	0	33	21	1	0	0	1	40042	16	16	2	25	80010	10	80000	10	80000	50	1840244	1	40033	40050	40060	29977	3	30020	80010	20	80000	20	160000	40049	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	8	80000	2	0	0	0	0	5020	3	16	3	4	40055	80000	10	40052	40060	40052	40060	40048
80024	40047	300	1	0	1	1	0	0	33	3	1	0	0	0	40035	0	16	0	25	80010	10	80000	10	80000	50	1839808	1	40024	40042	40047	29987	3	30027	80010	20	80000	20	160000	40051	40052	1	1	80021	10	9	10	10	80000	80000	10	80015	15	36	0	0	80014	1	0	20	80002	16	0	14	2	0	5020	4	16	4	4	40037	80000	10	40041	40043	40051	40043	40052
80024	40040	300	0	0	0	0	0	0	42	21	0	0	0	1	40037	0	16	6	25	80010	10	80000	10	80000	50	1840221	1	40032	40047	40051	29978	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	0	80002	0	34	0	0	0	5020	3	16	4	4	40047	80000	10	40060	40048	40059	40048	40059
80024	40051	300	1	0	1	0	0	0	12	3	1	0	0	0	40034	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	40017	40040	40060	29983	3	30031	80010	20	80000	20	160000	40059	40061	1	1	80021	10	9	10	10	80000	80000	10	80014	14	35	0	1	80014	1	0	14	80002	16	36	14	0	0	5020	5	16	3	4	40039	80000	10	40041	40043	40041	40043	40051
80024	40042	300	0	0	0	0	0	0	33	18	0	0	0	1	40032	16	15	1	25	80010	10	80000	10	80000	50	1839692	1	40026	40058	40059	29977	3	30031	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	0	80002	2	0	0	0	0	5020	5	16	5	5	40056	80000	10	40048	40059	40060	40048	40053
80024	40048	300	1	1	0	1	0	0	24	3	1	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40017	40050	40058	29982	3	30032	80010	20	80000	20	160000	40058	40050	1	1	80021	10	9	10	10	80000	80000	10	80014	14	36	0	0	80016	0	2	17	80002	16	36	14	1	0	5020	4	16	5	5	40039	80000	10	40043	40043	40043	40041	40048

STR (signed offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations