Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STR (signed offset, S)

Test 1: uops

Code:

  str s0, [x6, #0x10]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)030508090b1e1f22233a3f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a1a2a4a6a7a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
1005564411000181015391616225100010001000230280529554563367341210001000200056355411100110001000101514440110161161002164314173116115511000555555554553554
1004554411110181015371616025100010001000234381529552554367342110001000200056355411100110001000101515440110161171002164314173116115511000555555555554555
1004554410100190015391616125100010001000228840527554554364341210001000200055455211100110001000101615440210161161002164414173116115491000553553553564553
1004552411110190015391616125100010001000228841529553554367341010001000200055255411100110001000101515440010162161002164414073116115511000555555554552554
1004554411110170015391616225100010001000228840526555554365341210001000200055455111100110001000101614440210161191002164314073116115491000552553564555556
1004554411110181015481616125100010001000229081529553564367341010001000200055255411100110001000101415440110160161002164414173116115511000555556555555555
1004554410100181015491616525100010001000229560528554552367341010001000200055255411100110001000101415440010160181002164414173116115511000555555555553555
1004554410013181015391516125100010001000229081529554563367341010001000200055255411100110001000101515440010160171002164414273116115511000554552553564553
1004552410110181015391516225100010001000228840527554554364341210001000200055455311100110001000101415440010161181002164414273116115511000555555553553553
10045534110101050015401616225100010001000234380539552555367342110001000200055255411100110001000101416440110160161002164414073116115481000553552553564564

Test 2: throughput

Count: 8

Code:

  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  str s0, [x6, #0x10]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire (01)cycle (02)030508090b1e1f22233a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
802054005429910010171014003901622580100100800001248000050018399560400294004740053299643300058010020080000200160000400644005211802011009910010080000800001008001514440280016001680002164414151101161140049800001004006540048400534005540048
802044005430010110140014003701652580100100800001008000050018396920400274005440054299673300218010020080000200160000400544005411802011009910010080000800001008001415440180014001480000144414151101161140048800001004006440055400644005540056
80204400473001011618101400490160258010010080000100800005001839692040028400544005429967330010801002008000020016000040052400541180201100991001008000080000100800161500280014012080000164414251101161140051800001004005540048400554004840055
8020440048299101101400140049161602580100100800001008000050018396920400294005240053299603300128010020080000200160000400524005411802011009910010080000800001008001515440280014001480002164414151101161140051800001004004840048400484004840053
8020440054300100101910140039161622580100100800001008000050018400040400294005140047299603300058010020080000200160000400524005411802011009910010080000800001008001414440180016021880000164414051101161140051800001004004840064400484005340048
8020440064300110101800140032001258010010080000100800005001840004040029400474004729966330005801002008000020016000040052400541180201100991001008000080000100800141400080016001980002164414051101161140051800001004005540048400554004840048
802044005230010100140014003816162258010010080000100800005001839692040029400644005229960330012801002008000020016000040052400471180201100991001008000080000100800141500080014003380000164414151101161140051800001004005240055400534005540053
802044005430011000190014003716164258010010080000100800005001840438040030400474004729967330005801002008000020016000040054400641180201100991001008000080000100800141500080016021680000164414051101161140051800001004004840056400544004840053
80204400473001000018101400320162258010010080000100800005001840028040022400534004729967330005801002008000020016000040054400541180201100991001008000080000100800141500280014001480000164414051101161140060800001004004840055400544005540053
80204400543001011019101400391501258010010080000100800005001840004040022400474004729967330005801002008000020016000040054400471180201100991001008000080000100800151544008001401208000024414051101161140050800001004005240055400524005540064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)030508090b18191e1f2223243a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
800254005030000000010819100040038160425800101080000108000050184022014002240049400572997533003280010208000020160000400584005011800211091010800008000010800151536018001610208000216014105020316334004980000104005340059400484006040051
800244005930011010036181000400441614025800101080000108000050184029214003640053400522997533002280010208000020160000400494004211800211091010800008000010800000340080000008800002340005020516434005080000104004840059400524004840061
80024400593001000003003100040027160025800101080000108000050183942414002240061400582997733002080010208000020160000400424004211800211091010800008000010800000340080002002800022340005020416424004480000104005840048400594004840048
8002440053300100000243100040027160025800101080000108000050184019314001740050400472998233003280010208000020160000400574004711800211091010800008000010800151536008001600178000216014105020416554003980000104005240043400524004340043
80024400423000000003321100140042161622580010108000010800005018402441400334005040060299773300208001020800002016000040049400421180021109101080000800001080000034008000200880000200005020316344005580000104005240060400524006040048
8002440047300101100333100040035016025800101080000108000050183980814002440042400472998733002780010208000020160000400514005211800211091010800008000010800151536008001410208000216014205020416444003780000104004140043400514004340052
8002440040300000000422100014003701662580010108000010800005018402211400324004740051299783300228001020800002016000040042400401180021109101080000800001080000000080000000800020340005020316444004780000104006040048400594004840059
800244005130010100012310004003416160258001010800001080000501839424140017400404006029983330031800102080000201600004005940061118002110910108000080000108001414350180014101480002163614005020516344003980000104004140043400414004340051
80024400423000000003318000140032161512580010108000010800005018396921400264005840059299773300318001020800002016000040042400421180021109101080000800001080000034008000200080002200005020516554005680000104004840059400604004840053
800244004830011010024310004002716160258001010800001080000501839352140017400504005829982330032800102080000201600004005840050118002110910108000080000108001414360080016021780002163614105020416554003980000104004340043400434004140048