Firestorm: STUR (D) measurements

Code:

  stur d0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	6	3	1	0	539	16	16	0	25	1000	1000	1000	22448	1	517	542	543	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	1	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	544	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22472	1	517	542	542	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	551	1000	544	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22472	1	518	543	542	355	3	400	1000	1000	2000	554	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	540	1000	543	543	543	543	543
1004	542	3	0	3	1	0	539	16	16	1	25	1000	1000	1000	22472	0	518	543	543	355	3	412	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	543	543	543	543
1004	542	4	6	3	1	0	527	16	16	1	25	1000	1000	1000	22448	1	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	528	16	16	0	25	1000	1000	1000	23000	1	517	542	542	356	3	401	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	544	543	543	543	543
1004	542	4	6	3	1	0	539	16	16	1	25	1000	1000	1000	22448	1	517	542	542	355	3	401	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	543	543	543	543
1004	542	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22472	1	517	542	542	356	3	400	1000	1000	2000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	540	1000	543	544	544	544	544
1004	543	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22448	1	517	542	542	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	543	543	543	543
1004	554	4	0	3	1	0	527	16	16	0	25	1000	1000	1000	22448	1	517	542	543	356	3	401	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	2	2	539	1000	543	543	543	543	543

Count: 8

Code:

  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	40024	40042	40042	29955	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80002	2	34	5110	0	2	16	2	2	40039	0	80000	100	40601	40043	40052	40043	40041
80204	40042	300	0	0	18	9	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839760	40017	40042	40050	29962	3	30000	80100	200	80000	200	160000	40042	40050	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80002	2	34	5110	0	2	16	2	2	40039	0	80000	100	40050	40043	40051	40043	40041
80204	40042	300	0	0	0	3	1	0	40035	16	16	0	25	80100	100	80000	100	80000	500	1839424	40017	40040	40040	29955	3	30000	80100	200	80121	204	160484	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80000	0	8	80002	2	34	5110	0	2	16	2	2	40037	0	80000	100	40043	40043	40043	40050	40043
80204	40042	300	0	0	0	9	0	0	40034	16	16	18	25	80100	100	80000	100	80000	500	1839424	40026	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80000	2	34	5110	0	2	16	2	2	40039	0	80000	100	40051	40043	40051	40043	40052
80204	40042	300	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839808	40017	40042	40050	29963	3	30000	80100	200	80000	200	160000	40049	40049	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	0	80002	0	34	5110	0	2	16	2	2	40039	0	80000	100	40052	40043	40041	40043	40052
80204	40042	300	0	0	6	9	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	40017	40042	40042	29955	3	30008	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	8	80002	2	34	5110	0	2	16	2	2	40039	0	80000	100	40043	40595	40043	40041	40050
80204	40042	300	0	0	18	3	1	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839424	40017	40042	40042	29955	3	29998	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	8	80000	2	34	5110	0	2	16	2	2	40039	0	80000	100	40050	40041	40043	40043	40059
80204	40042	300	0	0	0	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	40025	40042	40042	29955	3	30007	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80000	2	34	5110	0	2	16	2	2	40048	0	80000	100	40043	40050	40043	40043	40041
80204	40050	300	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	40015	40042	40042	29953	3	30000	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	2	80002	0	34	5110	0	2	16	2	2	40039	0	80000	100	40043	40051	40043	40050	40041
80204	40040	300	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839808	40017	40049	40049	29963	3	30000	80100	200	80000	200	160000	40050	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	34	80002	0	5	80002	2	34	5110	0	2	16	2	2	40039	0	80000	100	40043	40043	40043	40043	40041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	2	0	0	0	30	0	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839448	0	0	40017	40042	40042	29975	3	30023	80010	20	80000	20	160000	40042	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	44	0	0	80000	0	0	2	80002	0	42	0	0	5020	0	0	0	4	16	0	0	0	6	5	40040	0	80000	10	40041	40043	40047	40043	40041
80024	40042	300	0	0	0	0	0	0	0	0	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	0	40015	40040	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	44	0	0	80002	0	0	2	80002	2	42	0	0	5020	0	0	0	7	16	0	0	0	5	6	40039	0	80000	10	40043	40044	40050	40041	40043
80024	40042	300	0	0	0	0	0	0	0	3	0	0	0	40027	16	0	1	25	80010	10	80000	10	80000	50	1839448	0	1	40017	40040	40040	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	44	0	0	80000	1	0	2	80000	2	42	0	0	5020	0	0	0	5	16	0	0	0	6	5	40039	0	80000	10	40044	40043	40043	40043	40043
80024	40040	300	0	0	0	0	0	0	0	3	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839352	0	1	40017	40054	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	0	0	5	80002	2	42	0	0	5020	0	0	0	6	16	0	0	0	6	7	40051	0	80000	10	40043	40041	40043	40046	40041
80024	40042	300	0	0	0	0	0	0	0	0	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	1	40017	40040	40042	29975	3	30020	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	2	0	6	80002	2	42	0	0	5020	0	0	1	7	16	0	0	0	7	5	40037	0	80000	10	40043	41847	41852	41943	41570
80024	41563	312	2	1	0	0	15	14	1728	1235	1	0	0	42115	16	16	1031	325	80970	10	80840	10	81512	61	1911163	0	0	41799	42114	41152	31629	198	31754	81522	20	81694	20	163146	42264	42124	16	1	80021	10	9	10	10	80000	80000	10	80904	42	473	0	80962	2	0	11968	80949	2	0	0	0	5323	0	0	0	6	128	0	1	0	6	7	41817	0	80000	10	42134	42023	41290	42166	41574
80024	42264	312	2	0	0	1	16	15	2112	1147	0	0	0	40177	0	16	0	25	80010	10	80000	10	80000	50	1839448	0	1	40015	40042	40042	29977	3	30020	80010	20	80000	20	163388	41995	41745	13	1	80021	10	9	10	10	80000	80000	10	80180	0	264	2	80602	6	4	6424	80542	2	42	2	0	5283	0	0	0	7	137	0	0	0	7	6	41857	0	80000	10	41565	42025	42257	42074	42261
80024	42113	316	0	0	0	1	10	15	1992	1320	0	0	0	40996	16	0	949	265	80730	10	80000	10	80000	50	1839448	0	0	40015	40042	40040	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80540	0	236	3	80542	2	2	7302	80302	2	42	4	0	5075	0	0	0	8	24	0	0	0	6	6	40037	0	80000	10	40041	40047	40041	40041	40182
80024	41660	332	0	1	0	1	10	3	1320	267	0	0	0	40027	16	16	1	331	80010	10	80120	10	80000	50	1839472	0	1	40018	40043	40043	29977	3	30023	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	81200	42	616	0	81382	3	2	22607	81742	2	0	0	0	5747	0	0	0	14	331	0	0	0	9	15	44771	0	80000	10	45635	45713	45323	45594	45357
80024	45441	345	0	0	0	0	33	28	4575	1851	0	0	0	44365	16	16	2834	1225	82355	10	82400	10	84320	50	2033644	0	0	41483	44472	44883	29977	3	30022	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	80002	1	0	3	80002	2	42	0	2	5020	0	0	1	6	16	0	0	0	5	6	40040	0	80000	10	40052	40043	40043	40045	40043

STUR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations