Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STUR (D)

Test 1: uops

Code:

  stur d0, [x6, #1]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)031e1f22233f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a2a4a7a8acafbcdcache store miss (c0)cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
10055424631053916160251000100010002244815175425433563400100010002000542542111001100010001000421100202100224273216225391000544543543543543
10045424031052716160251000100010002247215175425423563400100010002000542542111001100010001000420100202100224273216225511000544543543543543
10045424031052716160251000100010002247215185435423553400100010002000554542111001100010001000420100202100224273216225401000543543543543543
10045423031053916161251000100010002247205185435433553412100010002000542542111001100010001000420100202100224273216225391000543543543543543
10045424631052716161251000100010002244815175425423553400100010002000542542111001100010001000420100202100224273216225391000543543543543543
10045424031052816160251000100010002300015175425423563401100010002000542543111001100010001000420100202100224273216225391000544543543543543
10045424631053916161251000100010002244815175425423553401100010002000543543111001100010001000420100202100224273216225391000543543543543543
10045424031052716160251000100010002247215175425423563400100010002000543542111001100010001000420100202100224273216225401000543544544544544
10045434031052716160251000100010002244815175425423563400100010002000542542111001100010001000420100202100224273216225391000543543543543543
10045544031052716160251000100010002244815175425433563401100010002000542543111001100010001000420100202100224273216225391000543543543543543

Test 2: throughput

Count: 8

Code:

  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f22243f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a2a7a8acafbcdcache store miss (c0)cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
802054004230000031040027161602580100100800001008000050018394244002440042400422995533000080100200800002001600004004040042118020110099100100800008000010080000348000202800022345110021622400390800001004060140043400524004340041
8020440042300001890040025161602580100100800001008000050018397604001740042400502996233000080100200800002001600004004240050118020110099100100800008000010080000348000202800022345110021622400390800001004005040043400514004340041
802044004230000031040035161602580100100800001008000050018394244001740040400402995533000080100200801212041604844004240042118020110099100100800008000010080000348000008800022345110021622400370800001004004340043400434005040043
8020440042300000900400341616182580100100800001008000050018394244002640042400422995533000080100200800002001600004004240042118020110099100100800008000010080000348000202800002345110021622400390800001004005140043400514004340052
802044004230000030040027161602580100100800001008000050018398084001740042400502996333000080100200800002001600004004940049118020110099100100800008000010080000348000200800020345110021622400390800001004005240043400414004340052
802044004230000690040027161602580100100800001008000050018394244001740042400422995533000880100200800002001600004004240042118020110099100100800008000010080000348000208800022345110021622400390800001004004340595400434004140050
8020440042300001831040025161602580100100800001008000050018394244001740042400422995532999880100200800002001600004004240042118020110099100100800008000010080000348000208800002345110021622400390800001004005040041400434004340059
802044004230000000040027161602580100100800001008000050018394244002540042400422995533000780100200800002001600004004240042118020110099100100800008000010080000348000202800002345110021622400480800001004004340050400434004340041
802044005030000030040027161602580100100800001008000050018394244001540042400422995333000080100200800002001600004004040040118020110099100100800008000010080000348000202800020345110021622400390800001004004340051400434005040041
802044004030000030040027161602580100100800001008000050018398084001740049400492996333000080100200800002001600004005040042118020110099100100800008000010080000348000205800022345110021622400390800001004004340043400434004340041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030708090b18191e1f2223243f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a2a4a6a7a8a9acafbcdcache store miss (c0)c2cdcfd0d2icache miss (d3)d5d6d9dadbddinst fetch restart (de)e0eald/st retires (ed)gpr retires (ef)f5f6f7f8fd
800254004230000200030000040025160025800101080000108000050183944800400174004240042299753300238001020800002016000040042400431180021109101080000800001080000440080000002800020420050200004160006540040080000104004140043400474004340041
800244004230000000000100400271616025800101080000108000050183944800400154004040042299773300208001020800002016000040042400421180021109101080000800001080000440080002002800022420050200007160005640039080000104004340044400504004140043
80024400423000000000300040027160125800101080000108000050183944801400174004040040299753300228001020800002016000040042400421180021109101080000800001080000440080000102800002420050200005160006540039080000104004440043400434004340043
8002440040300000000030004002701602580010108000010800005018393520140017400544004229977330022800102080000201600004004240042118002110910108000080000108000000080002005800022420050200006160006740051080000104004340041400434004640041
8002440042300000000000004002516002580010108000010800005018393520140017400404004229975330020800102080000201600004004340043118002110910108000080000108000000080002206800022420050200017160007540037080000104004341847418524194341570
800244156331221001514172812351004211516161031325809701080840108151261191116300417994211441152316291983175481522208169420163146422644212416180021109101080000800001080904424730809622011968809492000532300061280106741817080000104213442023412904216641574
8002442264312200116152112114700040177016025800101080000108000050183944801400154004240042299773300208001020800002016338841995417451318002110910108000080000108018002642806026464248054224220528300071370007641857080000104156542025422574207442261
80024421133160001101519921320000409961609492658073010800001080000501839448004001540042400402997533002280010208000020160000400424004211800211091010800008000010805400236380542227302803022424050750008240006640037080000104004140047400414004140182
800244166033201011031320267000400271616133180010108012010800005018394720140018400434004329977330023800102080000201600004004040040118002110910108000080000108120042616081382322260781742200057470001433100091544771080000104563545713453234559445357
800244544134500003328457518510004436516162834122582355108240010843205020336440041483444724488329977330022800102080000201600004004040040118002110910108000080000108000000080002103800022420250200016160005640040080000104005240043400434004540043