Firestorm: STUR (Q) measurements

Code:

  stur q0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	543	4	0	0	3	0	0	528	0	16	0	25	1000	1000	1000	22448	0	517	542	542	356	3	400	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	1	1	539	1000	543	543	543	543	555
1004	542	4	0	0	0	0	0	527	16	0	0	25	1000	1000	1000	22448	0	518	542	542	355	3	401	1000	1000	2000	542	540	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	541	543	543	543	543
1004	542	4	0	0	3	0	0	525	16	16	1	25	1000	1000	1000	22352	0	518	543	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	544	544	544	544	541
1004	543	4	0	0	7	0	0	525	16	16	0	25	1000	1000	1000	22448	0	517	542	542	355	3	400	1000	1000	2000	542	554	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	553
1004	540	4	0	0	0	0	0	525	16	16	0	25	1000	1000	1000	22472	0	517	542	543	356	3	400	1000	1000	2000	543	542	1	1	1001	1000	1000	1000	42	0	1000	0	0	1002	2	42	73	1	16	1	1	539	1000	544	544	544	544	544
1004	543	4	0	9	3	0	0	528	16	16	1	25	1000	1000	1000	22472	0	517	543	543	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	1002	2	42	73	1	16	1	1	539	1000	544	544	544	543	543
1004	542	3	0	0	3	0	0	528	16	0	0	25	1000	1000	1000	22472	0	518	543	540	353	3	400	1000	1000	2000	540	542	1	1	1001	1000	1000	1000	42	0	1000	0	0	1002	2	42	73	1	16	1	1	539	1000	541	541	543	544	544
1004	543	4	0	21	0	0	0	527	16	16	6	25	1000	1000	1000	22448	0	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	544	544	544
1004	543	4	0	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	0	515	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	0	1000	0	42	73	1	16	1	1	539	1000	543	543	541	543	555
1004	542	4	0	0	3	0	0	527	16	16	1	25	1000	1000	1000	22448	0	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	1	2	1002	2	42	73	1	16	1	1	539	1000	543	543	541	541	543

Count: 8

Code:

  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40043	300	0	3	1	40025	16	16	0	25	80100	100	80000	100	80000	500	1839692	40027	40054	40054	29960	3	30012	80100	200	80000	200	160000	40047	40054	1	1	80201	100	99	100	100	80000	80000	100	80015	14	44	0	80016	0	1	18	80002	16	44	14	2	0	5110	1	16	1	1	40044	80000	100	40041	40041	40043	40043	40043
80204	40042	300	0	3	1	40028	16	16	0	25	80100	100	80000	100	80000	500	1839448	40017	40043	40043	29955	3	30001	80100	200	80000	200	160000	40123	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	2	80002	0	42	0	0	0	5110	1	16	1	1	40039	80000	100	40598	41017	40638	40184	40044
80204	40042	300	12	3	1	40027	16	16	266	25	80100	100	80000	100	80000	500	1839352	40017	40042	40042	29955	3	29998	80100	200	80000	200	160000	40181	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	2	80002	2	42	0	0	0	5110	1	25	1	1	40039	80000	100	40043	40041	40043	40043	40044
80204	40040	300	0	0	1	40028	16	16	0	25	80220	100	80000	100	80000	500	1839448	40486	40181	40043	29955	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40039	80000	100	40596	40181	40041	40047	40044
80204	40043	300	0	3	1	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	40015	40042	40042	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	1	0	5	80002	2	42	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40041	40044	40043	40044
80204	40042	300	6	3	1	40027	16	0	0	25	80100	100	80000	100	80000	500	1839352	40018	40043	40042	29956	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	8	80002	2	42	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40043	40043	40043	40041
80204	40040	300	0	3	1	40308	16	16	2	55	80100	100	80000	100	80108	500	1839448	40018	40043	40042	29955	3	29998	80100	200	80000	200	160000	40181	40040	1	1	80201	100	99	100	100	80000	80000	100	80242	0	42	28	80002	2	2	2	80002	2	42	0	0	0	5110	1	16	1	1	40040	80000	100	40044	40043	40043	40044	40041
80204	40040	300	0	3	1	40025	16	0	1	25	80100	100	80000	100	80000	500	1839448	40015	40042	40042	29956	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	80002	0	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40037	80000	100	40041	40043	40044	40044	40044
80204	40043	300	0	3	1	40027	0	16	1	25	80100	100	80000	100	80000	500	1839472	40017	40042	40042	29956	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80000	1	0	0	80002	2	0	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40043	40043	40041	40041
80204	40042	300	0	3	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839352	40017	40042	40042	29955	3	30000	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80002	0	0	8	80002	2	42	0	0	0	5110	1	16	1	1	40040	80000	100	40044	40043	40043	40044	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d0	d2	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40058	300	1	0	1	0	0	0	0	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40026	40042	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	5	80002	2	34	0	5023	3	1	1	17	16	14	17	40039	0	80000	10	40043	40041	40043	40043	40043
80024	40050	300	1	0	1	0	0	0	0	3	0	1	0	40028	0	16	6	25	80010	10	80000	10	80000	50	1839352	0	40017	40040	40040	29977	3	30022	80010	20	80000	20	160000	40043	40043	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	1	0	2	80002	0	0	0	5020	0	0	0	17	16	17	18	40039	0	80000	10	40041	40043	40043	40043	40043
80024	40040	300	0	0	0	0	0	0	0	3	0	1	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839472	0	40017	40042	40042	29978	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5020	0	0	0	14	16	17	9	40039	0	80000	10	40045	40043	40041	40044	40043
80024	40040	300	0	0	0	0	0	0	6	3	0	0	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839472	0	40017	40042	40040	29975	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80000	0	0	2	80000	0	42	0	5020	0	0	0	17	16	16	8	40039	0	80000	10	40041	40043	40043	40041	40041
80024	40040	300	0	0	0	0	0	0	0	0	1	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839448	0	40017	40042	40042	29977	3	30022	80010	20	80000	20	160000	40054	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	5020	0	0	0	16	16	14	17	40040	0	80000	10	40041	40043	40043	40041	40041
80024	40042	300	0	0	0	0	0	0	6	0	1	0	0	40027	16	0	1	25	80010	10	80000	10	80000	50	1839352	1	40017	40042	40042	29977	3	30034	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	1	0	80002	0	0	0	80002	2	0	0	5020	0	0	0	17	16	17	17	40039	0	80000	10	40043	40044	40041	40043	40044
80024	40042	300	0	0	0	0	0	0	0	3	0	0	0	40025	0	16	0	25	80010	10	80000	10	80117	50	1839448	0	40015	40054	40042	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	0	0	5020	0	0	0	20	16	17	8	40039	0	80000	10	40043	40043	40041	40043	40043
80024	40042	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	0	40015	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80000	0	0	2	80002	0	42	0	5020	0	0	0	8	16	17	14	40037	0	80000	10	40041	40190	40193	40043	40043
80024	40043	299	0	0	0	0	0	0	0	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	40017	40054	40042	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	42	0	0	80000	0	0	2	80000	2	42	0	5020	0	0	0	17	16	9	17	40037	0	80000	10	40041	40041	40043	40041	40043
80024	40043	300	0	0	0	0	0	0	0	0	0	0	0	40029	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	40018	40043	40043	29975	3	30023	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	42	0	5020	0	0	0	17	16	17	17	40037	0	80000	10	40043	40043	40041	40043	40043

STUR (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations