Firestorm: STUR (S) measurements

Code:

  stur s0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd store (99)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	0	3	1	0	536	16	16	0	25	1000	1000	1000	22424	0	517	550	542	363	3	400	1000	1000	2000	550	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	75	2	16	2	2	548	1000	543	543	551	552	552
1004	542	3	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22424	1	517	542	542	355	3	400	1000	1000	2000	551	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	548	1000	543	543	552	552	543
1004	542	4	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22760	0	517	549	542	355	3	400	1000	1000	2000	542	550	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	2	16	2	2	539	1000	543	543	543	543	543
1004	542	4	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22424	0	526	542	542	364	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	546	1000	543	550	551	543	543
1004	542	4	0	0	3	1	0	535	16	16	0	25	1000	1000	1000	22856	0	517	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	539	1000	550	543	543	543	543
1004	542	4	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22424	1	517	550	542	362	3	400	1000	1000	2000	542	549	1	1	1001	1000	1000	1000	34	1002	8	1002	2	34	73	2	16	2	2	539	1000	543	543	543	543	543
1004	542	4	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22424	0	517	550	542	362	3	400	1000	1000	2000	549	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	548	1000	543	551	552	543	543
1004	542	4	0	0	3	1	0	527	16	16	0	25	1000	1000	1000	22424	0	517	542	551	355	3	409	1000	1000	2000	542	551	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	539	1000	543	543	543	551	552
1004	551	4	0	0	3	1	0	527	16	16	2	25	1000	1000	1000	22424	1	525	542	542	364	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	539	1000	543	543	543	552	552
1004	551	3	0	0	3	1	0	527	16	16	2	25	1000	1000	1000	22856	1	526	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	34	1002	2	1002	2	34	73	2	16	2	2	539	1000	543	543	543	543	543

Count: 8

Code:

  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	0	0	0	972	18	1	1	40037	0	16	0	25	80100	100	80000	100	80000	500	1840508	1	40029	40052	40047	29960	3	30013	80100	200	80000	200	160000	40063	40047	1	1	80201	100	99	100	100	80000	80000	100	80015	14	0	0	1	80016	0	0	15	80002	16	44	14	2	5110	1	16	1	1	40051	80000	100	40048	40048	40048	40055	40064
80204	40054	300	1	0	0	0	0	0	498	19	0	1	40120	16	16	1	25	80100	100	80000	100	80000	500	1839352	1	40015	40040	40042	29955	3	30005	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5110	1	16	1	1	40037	80000	100	40041	40041	40043	40043	40043
80204	40054	300	0	0	0	0	0	0	0	3	0	0	40025	0	0	0	25	80100	100	80000	100	80000	500	1839448	1	40015	40042	40040	29953	20	30001	80100	200	80000	200	160000	40040	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	0	80000	2	42	0	0	5110	1	16	1	1	40037	80000	100	40043	40041	40041	40041	40044
80204	40040	300	0	0	0	0	0	0	777	0	1	0	40027	16	16	1	55	80340	100	80000	100	80000	500	1839448	1	40015	40040	40042	29967	3	30000	80100	200	80000	200	160000	40043	40043	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	5	80000	2	42	0	0	5110	1	16	1	1	40051	80000	100	40048	40055	40054	40055	40052
80204	40047	300	1	1	1	1	0	0	795	17	0	1	40032	0	16	6	25	80100	100	80000	100	80000	500	1840438	0	40022	40054	40052	29961	3	30001	80100	200	80000	200	160000	40040	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	0	0	0	5110	1	16	1	1	40037	80000	100	40041	40041	40043	40041	40041
80204	40040	300	0	0	0	0	0	0	360	3	0	0	40025	16	0	1	25	80100	100	80000	100	80121	500	1839352	1	40017	40040	40040	29955	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80000	0	0	3	80002	2	0	0	0	5110	1	16	1	1	40044	80000	100	40048	40048	40053	40055	40053
80204	40054	300	1	1	1	1	0	0	48	14	0	1	40036	16	0	2	25	80100	100	80000	100	80000	500	1839692	1	40022	40047	40047	29960	3	29998	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	1	0	2	80000	2	0	0	0	5110	1	16	1	1	40040	80000	100	40044	40044	40041	40041	40041
80204	40042	300	0	0	0	0	0	0	0	3	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839448	1	40029	40040	40042	29953	3	30000	80100	200	80000	200	160000	40042	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	2	80000	0	42	0	0	5110	1	16	1	1	40048	80000	100	40064	40055	40053	40055	40055
80204	40054	300	1	1	1	0	0	0	819	14	1	1	40037	16	0	84	25	80100	100	80000	100	80000	500	1840028	1	40022	40047	40052	29976	3	30000	80100	200	80000	200	160000	40042	40040	1	1	80201	100	99	100	100	80000	80000	100	80000	0	42	0	0	80002	0	0	2	80002	2	42	0	0	5110	1	16	1	1	40040	80000	100	40041	40044	40043	40041	40043
80204	40040	300	0	0	0	0	0	0	768	3	1	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	1	40017	40042	40040	29953	3	30000	80100	200	80000	200	160000	40040	40042	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	0	80002	0	0	0	80000	0	0	0	0	5110	1	16	1	1	40040	80000	100	40043	40043	40043	40041	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	0	0	0	0	0	900	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	40017	40042	40040	29977	3	30022	80010	20	80000	20	160000	40050	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	5020	7	16	4	4	40039	80000	10	40041	40043	40041	40041	40043
80024	40040	300	0	0	0	0	0	0	804	9	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839424	1	40017	40042	40050	29985	3	30030	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80000	0	0	0	5020	2	16	2	4	40047	80000	10	40043	40043	40041	40050	40041
80024	40040	300	0	0	0	0	0	0	0	3	1	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40024	40042	40042	29975	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	2	80002	2	0	0	5020	4	16	2	4	40039	80000	10	40043	40050	40043	40051	40043
80024	40040	300	0	0	0	0	0	0	0	0	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839832	1	40026	40042	40042	29977	3	30038	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	0	0	5020	2	16	4	2	40047	80000	10	40041	40052	40043	40051	40043
80024	40040	300	0	0	0	0	0	0	0	9	1	0	40027	16	0	2	25	80010	10	80000	10	80000	50	1839856	1	40015	40042	40040	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	0	80002	0	34	0	5020	5	16	4	4	40039	80000	10	40041	40043	40043	40043	40043
80024	40042	300	0	0	0	0	0	0	0	3	1	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	40017	40050	40042	29975	3	30022	80010	20	80000	20	160000	40051	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	0	80000	2	34	0	5020	3	16	2	6	40037	80000	10	40043	40043	40043	40043	40043
80024	40042	300	0	0	0	0	0	0	0	3	1	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1839424	1	40015	40050	40042	29984	3	30022	80010	20	80000	20	160000	40051	40050	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80000	0	0	2	80002	2	0	0	5020	4	16	4	6	40039	80000	10	40051	40041	40041	40041	40041
80024	40042	299	0	0	0	0	0	0	6	9	1	0	40033	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	40017	40189	40049	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80000	2	34	0	5020	4	16	2	4	40039	80000	10	40043	40043	40041	40041	40043
80024	40049	300	0	0	0	0	0	0	0	3	1	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839832	1	40025	40040	40042	29977	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	11	80002	2	0	0	5020	2	16	2	4	40039	80000	10	40043	40041	40043	40043	40041
80024	40040	300	0	0	0	0	0	0	876	6	1	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839856	0	40017	40042	40040	29975	3	30020	80010	20	80000	20	160000	40042	40050	1	1	80021	10	9	10	10	80000	80000	10	80000	0	34	0	0	80002	0	0	2	80002	2	34	0	5020	6	16	4	4	40039	80000	10	40043	40050	40043	40041	40043

STUR (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations