Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

STUR (S)

Test 1: uops

Code:

  stur s0, [x6, #1]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire (01)cycle (02)030a1e1f22243f46494f51inst issue (52)~issue ld/st (55)~dispatch ld/st (58)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op ld/st (7d)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst fp/simd store (99)inst ldst (9b)a0a2a7acafbcdcache store miss (c0)cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)f5f6f7f8fd
1005542400310536161602510001000100022424051755054236334001000100020005505421110011000100010003410022100223475216225481000543543551552552
1004542300310527161602510001000100022424151754254235534001000100020005515421110011000100010003410022100223473216225481000543543552552543
1004542400310527161602510001000100022760051754954235534001000100020005425501110011000100010003410028100223473216225391000543543543543543
1004542400310527161602510001000100022424052654254236434001000100020005425421110011000100010003410022100223473216225461000543550551543543
1004542400310535161602510001000100022856051754254235534001000100020005425421110011000100010003410022100223473216225391000550543543543543
1004542400310527161602510001000100022424151755054236234001000100020005425491110011000100010003410028100223473216225391000543543543543543
1004542400310527161602510001000100022424051755054236234001000100020005495421110011000100010003410022100223473216225481000543551552543543
1004542400310527161602510001000100022424051754255135534091000100020005425511110011000100010003410022100223473216225391000543543543551552
1004551400310527161622510001000100022424152554254236434001000100020005425421110011000100010003410022100223473216225391000543543543552552
1004551300310527161622510001000100022856152654254235534001000100020005425421110011000100010003410022100223473216225391000543543543543543

Test 2: throughput

Count: 8

Code:

  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  stur s0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030508090b18191e1f223a3f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)dtlb miss (c1)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
80205400423000000009721811400370160258010010080000100800005001840508140029400524004729960330013801002008000020016000040063400471180201100991001008000080000100800151400180016001580002164414251101161140051800001004004840048400484005540064
802044005430010000049819014012016161258010010080000100800005001839352140015400404004229955330005801002008000020016000040042400421180201100991001008000080000100800000420080002002800022420051101161140037800001004004140041400434004340043
8020440054300000000030040025000258010010080000100800005001839448140015400424004029953203000180100200800002001600004004040043118020110099100100800008000010080000000080002000800002420051101161140037800001004004340041400414004140044
80204400403000000007770104002716161558034010080000100800005001839448140015400404004229967330000801002008000020016000040043400431180201100991001008000080000100800000420080002005800002420051101161140051800001004004840055400544005540052
8020440047300111100795170140032016625801001008000010080000500184043804002240054400522996133000180100200800002001600004004040040118020110099100100800008000010080000042008000200280002200051101161140037800001004004140041400434004140041
80204400403000000003603004002516012580100100800001008012150018393521400174004040040299553300008010020080000200160000400404004211802011009910010080000800001008000000008000000380002200051101161140044800001004004840048400534005540053
802044005430011110048140140036160225801001008000010080000500183969214002240047400472996032999880100200800002001600004004040042118020110099100100800008000010080000042008000210280000200051101161140040800001004004440044400414004140041
80204400423000000000300400251616025801001008000010080000500183944814002940040400422995333000080100200800002001600004004240042118020110099100100800008000010080000000080002002800000420051101161140048800001004006440055400534005540055
802044005430011100081914114003716084258010010080000100800005001840028140022400474005229976330000801002008000020016000040042400401180201100991001008000080000100800000420080002002800022420051101161140040800001004004140044400434004140043
802044004030000000076831040027161612580100100800001008000050018394481400174004240040299533300008010020080000200160000400404004211802011009910010080000800001008000000008000200080000000051101161140040800001004004340043400434004140043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030708090b18191e1f22243f46494f51inst issue (52)~issue int (53)~issue ld/st (55)~dispatch int (56)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map lookup int (7f)~map lookup ld/st (80)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst fp/simd store (99)inst ldst (9b)9fa0a1a2a4a6a7a8a9acafbcdcache store miss (c0)c2cfd5d6ddinst fetch restart (de)e0ld/st retires (ed)gpr retires (ef)f5f6f7f8fd
80025400423000000009003104002716160258001010800001080000501839352140017400424004029977330022800102080000201600004005040040118002110910108000080000108000003400800020028000223405020716444003980000104004140043400414004140043
800244004030000000080491040027160025800101080000108000050183942414001740042400502998533003080010208000020160000400404004211800211091010800008000010800000340080002002800000005020216244004780000104004340043400414005040041
8002440040300000000031040027016025800101080000108000050183942404002440042400422997533002280010208000020160000400424004011800211091010800008000010800000340080000002800022005020416244003980000104004340050400434005140043
80024400403000000000010400271616025800101080000108000050183983214002640042400422997733003880010208000020160000400424004011800211091010800008000010800000340080002002800022005020216424004780000104004140052400434005140043
80024400403000000000910400271602258001010800001080000501839856140015400424004029975330022800102080000201600004004240042118002110910108000080000108000003400800000008000203405020516444003980000104004140043400434004340043
80024400423000000000310400270160258001010800001080000501839424040017400504004229975330022800102080000201600004005140042118002110910108000080000108000003400800000008000023405020316264003780000104004340043400434004340043
8002440042300000000031040025016025800101080000108000050183942414001540050400422998433002280010208000020160000400514005011800211091010800008000010800000340080000002800022005020416464003980000104005140041400414004140041
800244004229900000069104003316160258001010800001080000501839424140017401894004929975330022800102080000201600004004240042118002110910108000080000108000003400800020028000023405020416244003980000104004340043400414004140043
800244004930000000003104002516160258001010800001080000501839832140025400404004229977330022800102080000201600004005040042118002110910108000080000108000003400800020011800022005020216244003980000104004340041400434004340041
8002440040300000000876610400271600258001010800001080000501839856040017400424004029975330020800102080000201600004004240050118002110910108000080000108000003400800020028000223405020616444003980000104004340050400434004140043