Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBHN2 (vector, 2D)

Test 1: uops

Code:

  subhn2 v0.4s, v1.2d, v2.2d
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306425482510001000100039831330183037303724153289510001000300030373037111001100004873116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037230822548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037240612548251000100010003983133018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  subhn2 v0.4s, v1.2d, v2.2d
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071004162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071013162329634100001003003830038300383003830038
102043003728200133629548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010010071012162229634100001003003830038300383003830038
102043003722509006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
10204300372240006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250016129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012163229634100001003003830038300383003830038
10204300372250906129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722411001888167295482510010101000010100005042773131300183003730037282873287671001020100002030489300373008411100211091010100001000642816992963010000103003830038300383003830038
1002430037225110000267295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000642916862963010000103003830038300383003830038
10024300372251100001672954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006421016782963010000103003830038300383003830038
1002430037225110000167295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000644816992963010000103003830038300383003830038
10024300372241100302672954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006427168102963010000103003830038300383003830038
1002430037225110490288295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000642816862963010000103003830038300383003830038
1002430037225110000167295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000642916782963010000103003830038300383003830038
100243003722411000019702954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010006429161092963010000103003830038300383003830038
1002430037224110000167295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000642816882963010000103003830038300383003830038
1002430037225110000167295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000642616882963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  subhn2 v0.4s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e2a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071021611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731330018300373003728265328745101002041000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430084226000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300863003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038
10204300372250002322954825101001001000010010000500427731330018300373003728265328745101002001000020030000300373003711102011009910010010000100000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250006129548251001010100001010000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640516552963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640516552963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640516542963010000103003830038300383003830038
10024300372250006129548251001010100001210000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640516452963010000103003830038300383003830038
100243003722500013429548251001010100001010000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640516552963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640416542963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018030037300372828703287671001020100002030000300373003711100211091010100001000640516452963010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018030037300372828703287671001020100002030000300373003711100211091010100001000640724652970210000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018030037300372828703287671001020100002030000300373003711100211091010100001000640532542963010000103008530038300383003830038
10024300372250006129548251001010100001010000504277313030065030037300372828703287671001020100002030000300373003711100211091010100001000640416452963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  subhn2 v0.4s, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250082295482510100100100001251000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000097101161129634100001003003830038300383003830038
102043003722500774295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372259061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000107101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003022830037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372240061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826503287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000109640216222963010000103003830038300843003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640216222963010000103003830038300383003830038
1002430037225000082295482510010101000010100005042773130300183003730037282870328767100102010000203000030037300371110021109101010000100640225222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  subhn2 v0.4s, v8.2d, v9.2d
  movi v1.16b, 0
  subhn2 v1.4s, v8.2d, v9.2d
  movi v2.16b, 0
  subhn2 v2.4s, v8.2d, v9.2d
  movi v3.16b, 0
  subhn2 v3.4s, v8.2d, v9.2d
  movi v4.16b, 0
  subhn2 v4.4s, v8.2d, v9.2d
  movi v5.16b, 0
  subhn2 v5.4s, v8.2d, v9.2d
  movi v6.16b, 0
  subhn2 v6.4s, v8.2d, v9.2d
  movi v7.16b, 0
  subhn2 v7.4s, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l1i tlb fill (04)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420088150139258010010080000123800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641510392580100100800001008000050064000002004520064200644022801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
160204200641510609258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400001200452006420064322801002008000020024000020064200641116020110099100100160000100001011111611200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6erob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242007715012000057278001212800001280000626400001102003220051200510322800122080000202400002005120051111600211091010160000100000100383110202521116152005722001160000102005220061200522005220052
160024200511501200006327800121280000128000062640000110200322005120051032280012208000020240000200512005111160021109101016000010000010038311015252111592004822001160000102015420052201422005220052
1600242005115000000045298001212800001280000626400000102004120053200510322800122080000202400002005120051111600211091010160000100000100403111152721115142005022001160000102005420054200542005420054
16002420053150210001645278001212800001280000626400001102003420053200530322800122080000202400002005120051111600211091010160000100000100383110152541111182004822001160000102005220052200522005220052
160024200511501200006327800121280000128000062640000110200322005120051032280012208000020240000200512005111160021109101016000010000010039311093421214142005722001160000102005220052200522005220052
1600242005115022000045278001212800001280000626400001102003220051200510322800122080000202400002005120051111600211091010160000100000100378210172521117172004822001160000102005220052200612005220052
1600242005115012000045278001212800001280000626400001152004120051200510322800122080000202400002005120060111600211091010160000100000100388210162521115162004822001160000102005220052200522005220052
1600242005115212000051278001212800001280000626400001152003220051200510322800122080000202400002005120051111600211091010160000100300100388210172521115162004822001160000102005220061200612006120052
1600242005115111000051278001212800001280000626400001152003220051200510322800122080000202400002005120051111600211091010160000100000100388210162521117152004822001160000102005220052200522005220052
16002420051151010021045278001212800001280000626400001152003220051200510322800122080000202400002005120051111600211091010160000100000100398210162521115162004822001160000102005220052200522006120052

Test 6: throughput

Count: 16

Code:

  subhn2 v0.4s, v16.2d, v17.2d
  subhn2 v1.4s, v16.2d, v17.2d
  subhn2 v2.4s, v16.2d, v17.2d
  subhn2 v3.4s, v16.2d, v17.2d
  subhn2 v4.4s, v16.2d, v17.2d
  subhn2 v5.4s, v16.2d, v17.2d
  subhn2 v6.4s, v16.2d, v17.2d
  subhn2 v7.4s, v16.2d, v17.2d
  subhn2 v8.4s, v16.2d, v17.2d
  subhn2 v9.4s, v16.2d, v17.2d
  subhn2 v10.4s, v16.2d, v17.2d
  subhn2 v11.4s, v16.2d, v17.2d
  subhn2 v12.4s, v16.2d, v17.2d
  subhn2 v13.4s, v16.2d, v17.2d
  subhn2 v14.4s, v16.2d, v17.2d
  subhn2 v15.4s, v16.2d, v17.2d
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044004830000000480161025160117100160017100160000558128000040020400404004019973319997160100200160000200480000400484003911160201100991001001600001000000010110116114003601600001004004040072400404004040040
160204400403000000000041025160100100160000100160000500128000040020400394004819973319997160100200160000200480000400394003911160201100991001001600001000000010110116114004501600001004004040041400404004040041
1602044004830000000540141025160117100160061100160000500239902740021400394003919973319997160100200160000200480000400394004911160201100991001001600001000000010110116114003601600001004005040049400404005040041
1602044003929900001001741025160100100160000100160000500239899940021400484003919973319997160100200160000200480000400394003911160201100991001001600001000000010110160114003601600001004004040050400494004040040
160204400393000000030017148025160100100160477100160000500128000040020400394003919973319997160100200160000200480000400404003911160201100991001001600001000010010110116114003601600001004004040041400404004040040
1602044004030000000001741025160100100160017100160000500132000040020400394019819973319997160100200160000200480000400394003911160201100991001001600001000040010110116114003601600001004005040049400404005040040
160204400712990000000041025160161100160000100160000500239902740034400394004919973319997160100200160000200480000400494003911160201100991001001600001000000010110116114003601600001004004040049400404005040050
160204400393010000000083025160117100160001100160000500128000040030400394003919973319997160100200160000200480000400394003911160201100991001001600001000020010110116114004501600001004005040040400504004040049
1602044004830000000000520251601001001600011001600005001280000400214003940048199733200071601002001600002004800004022340039111602011009910010016000010000000101101161140046231600001004004040050400404004040040
1602044003930000000171881741025160402100160000100160000500538718840053400494027719973319997160100200160000200480000400394003911160201100991001001600001000000010110116114003601600001004005040040400404005040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)1e373a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244006730000100064251600101016000110160000502398999015400200400394003919996320028160010201600002048000040040400391116002110910101600001000001002283132162112926400362060160000104004040049400494004940049
1600244004830000000046251600271016001710160000501280000115400210400404004919996320019160010201600002048000040040400391116002110910101600001000001002283115162112816400452090160000104004040050400494004040049
16002440048311000000214251600111116011310160000501280000015400213400484003919996320020160010201600002048000040048400401116002110910101600001000301002283127162121528400362071160000104004040040400404004140040
16002440039300000017055251600111016000010160000602398999115400200400394003919996320019160010201602432048000040048400401116002110910101600001000001002284127162112828400452065160000104004140040400414004040041
1600244004030000001046251600101016001710160000501280000115400290400484004819996320019160010201600002048000040039400391116002110910101600001000001002282320162112722400372090160000104004040041400404004140041
16002440039300000017047251600271016001710160000501280000115400200400394003919996320028160010201600002048000040039400391116002110910101600001000001002283127162112828400372064160000104004040040400504004040049
16002440049300000000259251600101016000010160000501320000115400210400404004819996320028160010201600002048000040039400481116002110910101600001000001002283127162112727400362061160000104004040040400404004940041
16002440039300000017051251600101016000010160000502398999115400290400484004819996320028160010201600002048000040048400391116002110910101600001000001002283128162112726400362091160000104004940049400494004040040
1600244003929900000046251600101016000010160000502398999115400200400404003919996320019160010201600002048000040039400401116002110910101600001000001002283128162112327400374161160000104004040041400404004140040
1600244003930010001055251600101016000010160000501280000115400210400394004019996320019160010201600002048000040039400391116002110910101600001000001002282127162111726400362061160000104004940050400404004140050