Firestorm: SUBHN (vector, 2D) measurements

Code:

  subhn v0.2s, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	240	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	60	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	51	3	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	9	84	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	19	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  subhn v0.2s, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	136	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	2	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	3	10000	100	30085	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	0	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	2	2	29630	2	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	359	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	3	0	640	2	16	2	2	29630	0	10000	10	30038	30228	30038	30133	30038
10024	30131	225	0	0	0	45	170	29548	25	10010	12	10000	12	10000	50	4277313	0	30018	30037	30037	28287	3	28843	10010	20	10000	20	20324	30037	30131	3	1	10021	10	9	10	10	10000	10	2	2	1	5518	2	681	4	40	3	4	29630	2	10000	10	30038	30132	30180	30132	30227
10024	30181	226	1	1	1	267	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	1	0	0	61	29548	25	10012	12	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30134	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	4	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->3

Code:

  subhn v0.2s, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	102	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	770	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	29634	0	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	407	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	126	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	0	893	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	166	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30060	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	145	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	789	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	810	29548	25	10010	10	10000	10	10000	55	4278670	1	30054	30084	30085	28291	3	28787	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  subhn v0.2s, v8.2d, v9.2d
  subhn v1.2s, v8.2d, v9.2d
  subhn v2.2s, v8.2d, v9.2d
  subhn v3.2s, v8.2d, v9.2d
  subhn v4.2s, v8.2d, v9.2d
  subhn v5.2s, v8.2d, v9.2d
  subhn v6.2s, v8.2d, v9.2d
  subhn v7.2s, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20048	150	63	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	1	5110	2	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	150	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	151	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	41	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	62	25	80100	100	80000	100	80000	500	640000	20020	20039	20039	9973	0	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	5110	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20048	150	0	0	0	61	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5033	31	16	28	25	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80096	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	42	0	5041	28	16	22	29	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	105	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5037	28	16	21	28	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5037	25	16	17	28	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5043	26	16	28	27	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5037	28	16	29	26	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5040	13	16	27	15	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	63	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5037	28	16	29	22	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5037	28	16	29	29	20036	0	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	5037	24	16	21	24	20036	0	80000	10	20040	20040	20040	20040	20040

SUBHN (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations