Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBHN (vector, 2D)

Test 1: uops

Code:

  subhn v0.2s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372302406125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100006073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100051373116112630100030383038303830383038
10043037220984254825100010001000398313030183037303724153289510001000200030373037111001100019073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  subhn v0.2s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001001071011611296340100001003003830038300383003830038
102043003722500001362954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037211020110099100100100001000071011611296340100001003003830038300383003830038
10204300372240000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296343100001003008530038300383003830038
10204300372240000612954825101001001000010010000500427731313001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250000612954825101001001000010010000500427731303001803003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000612954825100101010000101000050427731303001830037300372828732876710012201000020200003003730037111002110910101000010000006404162229630210000103003830038300383003830038
100243003722500003592954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010001306402162229630010000103003830228300383013330038
1002430131225000451702954825100101210000121000050427731303001830037300372828732884310010201000020203243003730131311002110910101000010221551826814403429630210000103003830132301803013230227
1002430181226111267612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006403162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006422162229630010000103003830038300383003830038
10024300372250100612954825100121210000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038301343003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000822954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006424162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  subhn v0.2s, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
1020430037224010229548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
1020430037225077029548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100000710216222963400100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250007262954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250004072954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010036402162229630010000103003830038300383003830038
10024300372250001262954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372241008932954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010106402162229630010000103003830038300383003830038
10024300372250001662954825100101010000101000050427731313001830037300372828732876710010201000020200003006030037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250001452954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250007892954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
10024300372250008102954825100101010000101000055427867013005430084300852829132878710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  subhn v0.2s, v8.2d, v9.2d
  subhn v1.2s, v8.2d, v9.2d
  subhn v2.2s, v8.2d, v9.2d
  subhn v3.2s, v8.2d, v9.2d
  subhn v4.2s, v8.2d, v9.2d
  subhn v5.2s, v8.2d, v9.2d
  subhn v6.2s, v8.2d, v9.2d
  subhn v7.2s, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420048150632580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100151102161120036800001002004020040200402004020040
80204200391501502580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039151412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150412580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150622580100100800001008000050064000020020200392003999730399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500006125800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050333116282520036080000102004020040200402004020040
800242003915000040258001010800961080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001042050412816222920036080000102004020040200402004020040
800242003915000010525800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050372816212820036080000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050372516172820036080000102004020040200402004020040
80024200391500004025800101080000108000050640000020020200392003999963100198001020800002016000020039200391180021109101080000100050432616282720036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050372816292620036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050401316271520036080000102004020040200402004020040
80024200391500006325800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050372816292220036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050372816292920036080000102004020040200402004020040
80024200391500004025800101080000108000050640000120020200392003999963100198001020800002016000020039200391180021109101080000100050372416212420036080000102004020040200402004020040