Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (vector, 16B)

Test 1: uops

Code:

  sub v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000673116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110004073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100001273116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100001273116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000673116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sub v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420085150061196872510100100100001001000050028476800200182003720084184223187451010020010000200200002003720037111020110099100100100001000001007101161119814100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100020415307101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000001607101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150090196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000001307101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020210099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500132611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010030000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150005361968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150002561968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010013000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010020000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010020000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100390000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sub v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000000133196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197915100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000084196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010483640216221978510000102003820038200382003820038
10024200371501261196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216231978510000102003820038200382003820038
1002520037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500251196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500251196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sub v0.16b, v8.16b, v9.16b
  sub v1.16b, v8.16b, v9.16b
  sub v2.16b, v8.16b, v9.16b
  sub v3.16b, v8.16b, v9.16b
  sub v4.16b, v8.16b, v9.16b
  sub v5.16b, v8.16b, v9.16b
  sub v6.16b, v8.16b, v9.16b
  sub v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150000000292580108100800081008002050064013202001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511821622200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511811612200350800001002003920039200392003920039
80204200381500000001152580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511811612200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511821612200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013202001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511821621200350800001002003920039200392003920039
8020420038150000000522580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511811621200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511821621200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511811622200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511821622200350800001002003920039200392003920039
8020420038150000000292580108100800081008002050064013212001920038200389977699898012020080032200160064200382003811802011009910010080000100000000111511811622200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)daddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000392580010108000010800005064000002001920038200389996310018800122080000201600002003820038118002110910108000010000502023160252520035980000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800122080000201600002003820038118002110910108000010000502023160252620035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800122080000201600002003820038118002110910108000010000502026160262720035080000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800122080000201600002003820038118002110910108000010000502025160162720035080000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800122080000201600002024220038118002110910108000010000502027160272620035080000102003920039200392003920039
80024200381500004192580010108000010800005064000012001920038200389996310018800122080000201600002003820038118002110910108000010000502027160242620035080000102003920039200392003920039
8002420038150000832580010108000010800005064000012001920038200389996310018800122080000201600002003820038118002110910108000010000502020160262620035080000102003920039200392003920039
8002420038150000832580103128000012800005064152812001920038200389996310018800122080000201600002003820038118002110910108000010000502021160261520035080000102003920039200392003920039
8002420038150000812580010108000010800005064000012001920038200389996310018800122080000201600002003820038118002110910108000010000502014160271520035080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800122080000201600002003820038118002110910108000010000502027160252520035080000102003920039200392003920039