Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (vector, 2D)

Test 1: uops

Code:

  sub v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715096116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000094116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073127111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sub v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037161000120061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000040071011611197910100001002003820038200382003820038
10204200371610001200103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000371011611197910100001002003820038200382003820038
1020420037161000000103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000030371011611197910100001002003820038200382003820038
1020420037156000000726196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010371011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003716100000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715300000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
102042003715300000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
1020420037153000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000002771011611197910100001002003820038200382003820038
102042003715300000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000020071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640516531978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010009640516541978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000104603640516551978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416451978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200842003718444318767100102010000202000020037200371110021109101010000102200640516451978510000102003820038200382003820038
100242003715011061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001001163640416541978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010120177640516541978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010009640516451978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010003640516541978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010009640516551978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sub v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715900611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010003307101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000010807101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006403162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100236402242219785010000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001003206402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100136402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500008219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100106402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sub v0.2d, v8.2d, v9.2d
  sub v1.2d, v8.2d, v9.2d
  sub v2.2d, v8.2d, v9.2d
  sub v3.2d, v8.2d, v9.2d
  sub v4.2d, v8.2d, v9.2d
  sub v5.2d, v8.2d, v9.2d
  sub v6.2d, v8.2d, v9.2d
  sub v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051102161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500092225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000030051101161120035800001002003920039200392003920039
8020420038150104025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500060725801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001002010051271161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100050200021603220035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100050200041604320035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100050200031604220035080000102003920039200392003920039
80024200381500000392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001003650200031604420035080000102003920039200392003920039
8002420038149000039258001010800001080000506400001020019200392004799963100188001020800002016000020038200381180021109101080000100050200041622420035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100050200021604420035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100050200041604420035080000102003920039200392003920039
80024200381490000392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001007250200021602220035080000102003920039200392003920039
80024200381500000609258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000101050200021602320035080000102003920039200392003920039
800242003815000003925800101080000108000050640000102001920038200389996310018800102080000201600002003820038118002110910108000010010550200031602320035080000102003920039200392003920039