Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (vector, 4S)

Test 1: uops

Code:

  sub v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371608416872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
1004203715728216872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371508216872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sub v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000000103196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
102042003715001000000189196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038
10204200371500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640416221978510000102003820038200382003820038
100242003715000000082196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000000061196872510010111000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640116221978510000102003820038200382003820038
100242003715000000082196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150000000145196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sub v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021641197910100001002003820038200382003820038
10204200371490000000726196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
1020420037150000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000000421196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000710225111993325100001002027820279202282013520276
102042018116300326633520227919632991019613410060130100006352852812020162202772022718430271881910727212108342162131820276202776110201100991001001000010022202824340802161221993019100001002003820275202282027820278
1020420275152004567244002008196431001010013110060134107606932852812020162202762027618426281883510730216106642002132220326202785110201100991001001000010044010391000828257111993430100001002027620180201832027920279
102042022915211446724400247219643119101961421004813910760693285409502016220179200851843625188371089520010832216216582022820277611020110099100100100001002221080180082511611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)0e18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500200906119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100001000640216221978510000102003820038200382003820038
100242003715000000014219687251006310100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820132
10024200371500000006119687251001010100121010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
100242003715000000010319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
1002420037160004679552830061962113710078141007219110647628553780202702022620369184634118930108702411328202230020369203259110021109101010000104401017452804472231996710000102003820038200382046220226
100242018015810001810831519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000030640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000102000000640216221978510000102003820038200382003820038
100242003715000000015119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sub v0.4s, v8.4s, v9.4s
  sub v1.4s, v8.4s, v9.4s
  sub v2.4s, v8.4s, v9.4s
  sub v3.4s, v8.4s, v9.4s
  sub v4.4s, v8.4s, v9.4s
  sub v5.4s, v8.4s, v9.4s
  sub v6.4s, v8.4s, v9.4s
  sub v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511041611200350800001002003920039200392003920039
8020420038150000000041625801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000017725801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
8020420038150000000070525801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715100392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050208160572003580000102003920039200392003920039
8002420038150001462580010108000010800005064000020019200382008699963100188001020800002016000020038200381180021109101080000100050207160772003580000102003920039200392003920039
800242003815000802580010108000010800005064000020019200382003899963100188001220800002016000020038200381180021109101080000100050204160652003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050207160772003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050207160652003580000102003920039200392003920039
800242003815000622580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050209160572003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050208160552003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050205160552003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050208160672003580000102003920039200392003920039
800242003815000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100050209160972003580000102003920039200392003920039