Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (vector, 8H)

Test 1: uops

Code:

  sub v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073316221787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
10042037150124168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715061167625100010001000264680120182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715082168725100010001000264680020182037203715723189510001000200020372037111001100000073216221787100020862038203820382038

Test 2: Latency 1->2

Code:

  sub v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372018111102011009910010010000100007104161119791100001002003820038200382003820038
1020420037150091619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715096119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718433318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010710000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150015619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500012124196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715002061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003721100211091010100001012010640316341978510000102003820038200382003820038
100242003715000061196874310010101000010100005028476800200182003720084184447187671031820100002020000200372008521100211091010100001000640316331978510000102003820038200382003820038
10024200371500020761196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640516331978510000102003820038200382003820038
1002420037150001561196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500033103196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102013220038200382003820038
1002420085150001861196872510010101000010100005028476800200182003720037184493187671016320100002020000200372003711100211091010100001007728640316331978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150001561196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sub v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150036611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200104952002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150005361968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000017101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119858100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002012620037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000300611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000000611968725100101010000101000050284768020018200372003718444318767100102010837222165220274203216110021109101010000100020109970007454418419966410000102027320322202752027620322

Test 4: throughput

Count: 8

Code:

  sub v0.8h, v8.8h, v9.8h
  sub v1.8h, v8.8h, v9.8h
  sub v2.8h, v8.8h, v9.8h
  sub v3.8h, v8.8h, v9.8h
  sub v4.8h, v8.8h, v9.8h
  sub v5.8h, v8.8h, v9.8h
  sub v6.8h, v8.8h, v9.8h
  sub v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511041611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381550000040258030110080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010001000511011611200840800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010001000511011611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010001000511011611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038150000007051148010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010007000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500442580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010221595020116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010035020116112003580000102003920039200392003920039
800242003815003925800101080185108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100155020116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020216112003580000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001011055020116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020116112003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010835020116112003580000102003920039200392003920039
800242003815003925800101180000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100185020116112003580000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000101155020116112003580000102003920039200392003920039