Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (vector, D)

Test 1: uops

Code:

  sub d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150711687251000100010002646801201820372037157231895100010002000203720371110011000000073216111787100020382038203820382038
10042037160611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000004873116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000179373116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000673116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037160611687251000100010002646801201820372037157231895100010002000203720371110011000001073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sub d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715084619687251010010010000100100005002847680020018200372003718422031874510100204100002002000020037200371110201100991001001000010003071011611197910100001002003820038200382003820038
1020420037150105419687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715089719687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611198680100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422031874510100200100002002034420037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371496119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010003071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000002291968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000020606402162219785010000102003820038200382003820038
100242003715000000003611968725100101010000101000050284768002001820084200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000821968725100101010000101000050284768002001820037200371844431876710162201000020200002003720037111002110910101000010000000306402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000003606306402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sub d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500107196872510100100100001001000050028476800200182003720037184296187411010020010008200200162003720037111020110099100100100001000071021611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001006071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500124196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037149061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150082196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000010319687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000100640316331978510000102003820038200382003820038
100242003715000000061019687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640316331978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640316331978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640316331978510000102003820038200382003820038
100242003715011100014519687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000009640316331978510000102003820038200382003820038
1002420037150000000123119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000100640316331978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100221091010100001000000640316331978510000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640316331978510000102003820038200382003820038
100242003715000000014919687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000003640316331978510000102003820038200382003820038
10024200851500000008419687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000000640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sub d0, d8, d9
  sub d1, d8, d9
  sub d2, d8, d9
  sub d3, d8, d9
  sub d4, d8, d9
  sub d5, d8, d9
  sub d6, d8, d9
  sub d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000030511021611200350800001002003920039200392003920039
802042003815000024004025801001058009510080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920185200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000400511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080110500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381500000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050201516112003580000102003920039200392003920039
80024200381510003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050201816112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050201016112003580000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050201216112003580000102003920039200392003920039
800242003815000070425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050201016112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050201316112003580000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020916112003580000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020816112003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050201016112003580000102003920039200392003920039