Firestorm: SUB (vector, D) measurements

Code:

  sub d0, d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	71	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	2	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	48	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	1793	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	6	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	1	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  sub d0, d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	846	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	204	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1054	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	897	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19868	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20344	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	229	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	6	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	361	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20084	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	82	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10162	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	36	0	63	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->3

Code:

  sub d0, d1, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	107	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18429	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	6	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	124	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	82	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	103	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	610	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	1	0	0	0	145	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	9	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	1231	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10022	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	149	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20085	150	0	0	0	0	0	0	84	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  sub d0, d8, d9
  sub d1, d8, d9
  sub d2, d8, d9
  sub d3, d8, d9
  sub d4, d8, d9
  sub d5, d8, d9
  sub d6, d8, d9
  sub d7, d8, d9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20057	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	3	0	5110	2	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	24	0	0	40	25	80100	105	80095	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20185	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	4	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80110	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	15	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	151	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	18	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	10	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	4	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	12	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	704	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	10	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	13	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	9	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	8	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	150	0	0	0	39	25	80010	10	80000	10	80000	50	640000	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	10	16	1	1	20035	80000	10	20039	20039	20039	20039	20039

SUB (vector, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations