Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUQADD (scalar, D)

Test 1: uops

Code:

  suqadd d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073216112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037233612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020863037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723216612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  suqadd d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020220000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100207102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282650328745101002001000020020000300373003711102011009910010010000100007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225009306129548251001010100071010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006404162229630010000103007430178300863003830038
100243003722500906129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225002706129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225004206129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225004506129548251001010100001010000504277313130018300373003728287328786100102010000202000030037300371110021109101010000100000006402162229699010000103003830038300383003830038
10024300372250015073729548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
1002430037225001506129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722400006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  suqadd d0, d0
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500061295472510100100100001001000050042771603001830037300372827172874010100200100082002001630037300371110201100991001001000010000001117170160029646100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771603001830037300372827162874010100200100082002001630037300371110201100991001001000010000001117180160029646100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771603001830037300372827162874110100200100082002001630037300371110201100991001001000010000001117180160029645100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300373110201100991001001000010000001117222242229629100001003003830038300383003830038
102043003722500197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
102043003722500197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010001001117222242229629100001003003830038300383003830038
102043003722509197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
102043003722400197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
102043003722500197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038
102043003722500197295472510100100100001001000050042771603001830037300372825262873310100200100002002000030037300371110201100991001001000010000001117222242229629100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000004506129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640416552962910000103003830038300383003830038
1002430037225000000053629547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640616562962910000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160130018300373003728300328767100102010000202000030037300371110021109101010000101000640516462962910000103003830038300383003830038
100243003722500000008229547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640616562962910000103003830038300383003830038
100243003722400000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640516562962910000103003830038300383003830038
10024300852250101208875229529251001010100001010300504277160130018300373003728286328767100102010325202033630037300372110021109101010000100000640616562962910000103021730180302763027430131
10024301782261015440506129538431001010100001010150504277160130018301803003728286828786101622210000202032630083300842110021109101010000100000640616652962910000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640516452962910000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640516552962910000103003830038300383003830038
100243003722500000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640616652962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd d0, d8
  movi v1.16b, 0
  suqadd d1, d8
  movi v2.16b, 0
  suqadd d2, d8
  movi v3.16b, 0
  suqadd d3, d8
  movi v4.16b, 0
  suqadd d4, d8
  movi v5.16b, 0
  suqadd d5, d8
  movi v6.16b, 0
  suqadd d6, d8
  movi v7.16b, 0
  suqadd d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009015100000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901610200621600001002006620066200662006620066
1602042006515100000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000005025801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515100000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000002925801161008001610080028500640196020045200652031761280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515100000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006215022005127800101080000108000050640000112003220051200513228001020800002016000020051200511116002110910101600001000100443112525211241420048201160000102005220052200522005220052
16002420051150220017727800101080000108000050640000112003220051200513228001020800002016000020051200511116002110910101600001001100453112234211212320048201160000102005220052200522005220052
1600242005115011005127800101080000108000050640000112003220051200513228001020800002016000020051200511116002110910101600001000100453112425211212320048201160000102005220052200522005220052
1600242005115001005127800101080000108000050640000112003220051200603228001020800002016000020060200511116002110910101600001000100433112434221232320048202160000102006120052200522005220052
1600242005115111005727800101080000108000050640000112003220376200513228001020800002016000020060200511116002110910101600001000100433111925411221920048201160000102006120061200612005220061
1600242005115001006729800101080000108000050640000112003220060200603228001020800002016000020051200511116002110910101600001000100486112225211202120048201160000102005220052200522006120052
1600242005115001004527800101080000108000050640000112003220051200513228001020800002016000020051200511116002110910101600001000100463112525211202320048202160000102005220052200612005220052
1600242005115021005729800101080000108000050640000112003220060200513228001020800002016000020051200601116002110910101600001000100456111525211241920048201160000102005220052200522005220052
1600242005115011005127800101080000108000050640000012004120060200513228001020800002016000020051200511116002110910101600001000100413112446212142020048201160000102005220052200522005220052
1600242005115031016329800101080000108000050640000112003220051200513228001020800002016000020051200511116002110910101600001000100443212234221232120048401160000102005220061200522005220052

Test 5: throughput

Count: 16

Code:

  suqadd d0, d16
  suqadd d1, d16
  suqadd d2, d16
  suqadd d3, d16
  suqadd d4, d16
  suqadd d5, d16
  suqadd d6, d16
  suqadd d7, d16
  suqadd d8, d16
  suqadd d9, d16
  suqadd d10, d16
  suqadd d11, d16
  suqadd d12, d16
  suqadd d13, d16
  suqadd d14, d16
  suqadd d15, d16
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440049300030251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
16020440039299030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
160204400392990695251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
16020440039299030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000091111011817400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040
160204400393000695251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011816400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003930011000000046251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002382114316111282940036165160000104004040040400404004040040
1600244003930001001000158251600101016000010160000501280000115400204003940039199963200191600102016000020320212400394003911160021109101016000010020001002482112216111282340036165160000104004040040400404004040040
16002440039300110110001107251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002482112116111303040036165160000104004040040402504004040040
16002440039300100100000107251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000311002382112516111252740036165160000104004040040400404004040040
160024400393001101100001372516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001201002482112116111252140036165160000104004040251400404004040040
16002440039300110100001149251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001004182112616111262640036165160000104004040040400404004040040
16002440039300110100001107251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002482112516111252640036165160000104004040040400404004040040
16002440039300110110001149251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002482112616111262640036165160000104004040040400404004040040
16002440039300110110000107251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002382111616111261840036165160000104004040040400924004040040
1600244003930010010000195251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000001002482111616111271840036165160000104004040040400404004040040