Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUQADD (vector, 4S)

Test 1: uops

Code:

  suqadd v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372208425482510001000100039831303018303730372415328951000100020003037303711100110000073216332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000116320003037303711100110003073316332630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372366125482510001000100039831313018303730372415328951148100020003037303711100110000073316332630100030383038303830383038
1004303723936125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
10043037233876125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073316332630100030383038303830383038

Test 2: Latency 1->1

Code:

  suqadd v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10205300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296900100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830230300372826532874510100200100002002000030037300371110201100991001001000010000710022511296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710511611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133005430037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773133001830037300372826532874510100200100002002000030037300371110201100991001001000010000710011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006404162229630010000103003830038300383003830038
1002430084225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037224000000612954825100101010000101000050427731303016230037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103008530038300383003830038
1002430037224000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000090612954825100101010000101000050427731313001830180300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010003006402162229630010000103032130180301803017930228
100243014222711334142642123295031061003515100401610447604282741130126302263013128295282887810460201049022209823022630309211002110910101000010000027306403162229648010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  suqadd v0.4s, v0.4s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240000061295472510100100100001001000050042771601301623003730085282716287411010020010008200200163003730037111020110099100100100001000400111761160296450100001003003830038300383003830038
1020430037225000120612954725101001001000010010000500427716013001830084300372827110287411010020010008200200163003730037111020110099100100100001000000111717160296450100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001000000111717160296450100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282716287401010020010008200200163003730037111020110099100100100001000000111718160296460100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771600300183003730037282717287401010020010008200200163003730037111020110099100100100001000000111718160296450100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771601300183008430037282717287411010020010008200200163003730037111020110099100100100001000003111718160296460100001003003830038300383003830038
102043003722500200293295472510100102100161001000051142771600300183003730179282716287401010020610008208200163003730037111020110099100100100001000000111717160296450100001003003830038300383003830038
10204300372240000061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001000003111717160296460100001003003830038300383003830038
10204300372250003061295472510100100100001001000050042771601300183003730037282716287401010020010008200200163003730037111020110099100100100001000000111718160296460100001003003830038300383003830038
10204300372250000061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001000000111717160296450100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372240612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250612954725100101010000101000050427716003016230037300372828632876710010201000020200003003730084111002110910101000010006403242229629010000103003830038300383003830038
10024300372250612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372250612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629310000103003830038300383003830038
10024300372250612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103008530038300383003830038
10024300372250612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038
10024300372240612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010006402162229629010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd v0.4s, v8.4s
  movi v1.16b, 0
  suqadd v1.4s, v8.4s
  movi v2.16b, 0
  suqadd v2.4s, v8.4s
  movi v3.16b, 0
  suqadd v3.4s, v8.4s
  movi v4.16b, 0
  suqadd v4.4s, v8.4s
  movi v5.16b, 0
  suqadd v5.4s, v8.4s
  movi v6.16b, 0
  suqadd v6.4s, v8.4s
  movi v7.16b, 0
  suqadd v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200911511100292580116100800161008002850064019612004502006520065612801282008002820016005620065200651116020110099100100160000100001111012331644200621600001002006620066200662006620066
1602042006515011033292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012341645200621600001002006620066200662006620066
160204200651511100292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012351654200621600001002006620066200662006620066
16020420065150110399292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012351655200621600001002006620066200662006620066
160204200651501100292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012341645200621600001002006620066200662006620066
16020420065150110312292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012251655200621600001002006620066200662006620066
16020420065151110456292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012341655200621600001002006620066200662006620066
1602042006515011002192580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012351654200621600001002006620066200662006620066
160204200651501100292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012241644200621600001002006620066200662006620066
160204200651501100292580116100800161008002850064019602004502006520065612801282008002820016005620065200651116020110099100100160000100001111012341635200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420082150004527800101080000108000050640000212003220051200513228001020800002016000020051200511116002110910101600001000010036622112521110720048201160000102005220052200522006120052
1600242005115002468278001010800001080000506400000120032200512005132280010208000020160000200512005111160021109101016000010000100336221034422101020057402160000102006120061201632006120061
16002420060150005129800101080000108000050640000312004120060200603228001020800002016000020060200511116002110910101600001000010030311102521171020048201160000102005220052200522005220052
16002420051151004529800101080000108000050640000002003220051200513228001020800002016000020051200511116002110910101600001000010030311102541110720048201160000102005220052200522005220052
160024200511500372512780010108000010800005064000031200322005120051322800102080000201600002005120051111600211091010160000100001003431172521171020048201160000102005220052200522005220052
16002420051151004527800101080000108000050640000302003220051200513228001020800002016000020051200511116002110910101600001000010033611102521171020048201160000102005220052200522005220052
160024200511500045278001010800001080000506400003120032200512005132280010208000020160000200512005111160021109101016000010000100333111025211101020048201160000102005220052200522006120061
16002420051150124452780010108000010800005064000001200322005120051322800102080000201600002005120051111600211091010160000100001003031172521171020048201160000102005220052200522005220052
16002420051150004527800101080000108000050640000012003220051200513228001020800002016000020051200511116002110910101600001000010033311102521110720048202160000102006120052200522005220052
16002420051155004527800101080000108000050640000012003220051200513228001020800002016000020051200511116002110910101600001000010031311102521110720048201160000102005220052200522005220052

Test 5: throughput

Count: 16

Code:

  suqadd v0.4s, v16.4s
  suqadd v1.4s, v16.4s
  suqadd v2.4s, v16.4s
  suqadd v3.4s, v16.4s
  suqadd v4.4s, v16.4s
  suqadd v5.4s, v16.4s
  suqadd v6.4s, v16.4s
  suqadd v7.4s, v16.4s
  suqadd v8.4s, v16.4s
  suqadd v9.4s, v16.4s
  suqadd v10.4s, v16.4s
  suqadd v11.4s, v16.4s
  suqadd v12.4s, v16.4s
  suqadd v13.4s, v16.4s
  suqadd v14.4s, v16.4s
  suqadd v15.4s, v16.4s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044005930000302516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
1602044009029900302516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811610400361600001004004040040400404004040040
1602044003929900352516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
1602044003930000302516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
160204400393000030251601081001600081001600205001280132400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000058301111011811611400361600001004004040040400404004040040
1602044003929900302516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
1602044003930000302516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
1602044003930000302516010810016000810116002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
1602044003930000302516010810016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040
1602044003930000302516018410016000810016002050012801324002040039400391997761999016012020016003220032006440039400391116020110099100100160000100000001111011811611400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400503000000046251600101016000010160000501280000114002004003940039199963200191600102016000020320000400394003911160021109101016000010100001002231161621169401271561160000104081240860412204121940861
1600244091531922400127251600101016000010160000501280000114002004003940039199963200191600102016000020320000400394003911160021109101016000010003001002231191621269400361550160000104004040040400404004040040
160024400393000003688115251600101016000010160000501280000114002004003940039199963200191600102016000020320000401284003911160021109101016000010000001002231191621169400361550160000104004040040400404004040040
160024400393000000046251600101016000010160000501280000114002004003940039199963200191600102016000020320000400394003911160021109101016000010000001002231171621199400361550160000104004040040400404004040040
160024400393000000046251600101016000010160000501280000114002004003940039199963200191600102016000020320000400394003911160021109101016000010000001002231191621196400361550160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800003140020040039400391999632001916001020160000203200004003940039111600211091010160000100000010024311101621196400361550160000104004040040400404004040040
16002440039300000002362516001010160000101600005012800001140020040039400391999632004816001020160000203200004003940039111600211091010160000100000010022311916211109400361550160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001140020040039400391999632001916001020160000203200004003940039111600211091010160000100000010022311101621197400361550160000104004040040400404004040040
160024400393000000046251600101016000010160000501280000014002004003940039199963200191600102016000020320000400394003911160021109101016000010000001002231191621196400361550160000104004040040400404004040040
1600244003930000000258251600101016000010160000501280000214002004003940039199963200191600102016000020320000400394008811116002110910101600001034030010022622916211694003615100160000104004040040400404004040040