Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUQADD (vector, 8B)

Test 1: uops

Code:

  suqadd v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723961254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100003073216222630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
10043037229961254825100010001000398313130183037303724153289510001000200030373037111001100001373216222630100030383038303830383038
100430372326761254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100002073216122630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303722061254825100010001000398313130183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303723361254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038
1004303722061254825100010001000398313030183037303724153289510001000200030373037111001100000073216222630100030383038303830383038

Test 2: Latency 1->1

Code:

  suqadd v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010001007102161129634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010003007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129635100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010004007101161129634100001003003830038300383003830038
102043003722400612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010006307101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000612954825100101010000101000050427731303001830037302252828732876710458201000020200003003730037111002110910101000010023000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722400000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722400000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  suqadd v0.8b, v0.8b
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500168295472510100100100001001000050042771601300180300373003728271628741101002001000820020016300373003711102011009910010010000100001117171629645100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300180300373003728271628740101002001000820020016300373003711102011009910010010000100001117181629645100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300180300373003728271628741101002001000820020016300373003711102011009910010010000100001117171629629100001003003830038300383003830038
10204300372240197295472510100100100001001000050042771601300180300373003728252628733101002001000020020000300373003711102011009910010010000100001117171629646100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300183300373003728271728741101002001000820020016300373003711102011009910010010000100001117171629646100001003003830038300383003830038
102043003722500170295472510100103100001001000050042771601300180300373003728271628740101002001000820020016300373003711102011009910010010000100001117171629646100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300180300373003728271628741101002001000820020016300373003711102011009910010010000100001117181629645100001003003830038300383003830038
102043003722500427295472510100100100001001000050042771601300180300373003728271728741101002001000820020016300373003711102011009910010010000100001117181629645100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771600300180300373003728271728740101002001000820020016300373003711102011009910010010000100001117181629645100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300180300373003728271728741101002001000820020016300373003711102011009910010010000100001117181629646100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129547251001910100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006406162229629010000103003830038300383003830038
10024300372250000006129547431001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250000006129538251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000104028106402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000102006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100006402162229629010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd v0.8b, v8.8b
  movi v1.16b, 0
  suqadd v1.8b, v8.8b
  movi v2.16b, 0
  suqadd v2.8b, v8.8b
  movi v3.16b, 0
  suqadd v3.8b, v8.8b
  movi v4.16b, 0
  suqadd v4.8b, v8.8b
  movi v5.16b, 0
  suqadd v5.8b, v8.8b
  movi v6.16b, 0
  suqadd v6.8b, v8.8b
  movi v7.16b, 0
  suqadd v7.8b, v8.8b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200901510000000013625801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016012006201600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016012006201600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196200450200652014861280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
160204200651500000000011525801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
16020420065150000000009225801161008001610080028500640196200453200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
16020420065150000000007125801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016022006201600001002006620066200662006620066
16020420065150000000002925801161008001610080028500640196200450200652006561280128200800282001600562006520065111602011009910010016000010000000011110119016012006201600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200851501051258001010800001080000506400001102002720050200463228001020800002016000020046200461116002110910101600001000100506219242021123322004715160000102004720047200472004720047
16002420046150107825800101080000108000050640000110200272005020046322800102080000201600002004620046111600211091010160000100010047311242042118302004315160000102004720051200472004720047
1600242004615011223258001010800001080000506400001102002720050200503228001020800002016000020046200461116002110910101600001000100473112420141120322004315160000102004720047200472004720047
16002420050150425125800101080000108000050640000110200272005020046322800102080000201600002004620046111600211091010160000100010046311232021121342004330160000102005120047200472004720051
16002420046150225725800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000100010045312232022224332004315160000102005120051200472004720047
16002420046151114525800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000100010049311252041124272004315160000102004720051200472004720047
16002420046150215125800101080000108000050640000110200272005020046322800102080000201600002004620046111600211091010160000100010047311242021125262004315160000102004720047200472004720047
16002420046150225125800101080000108000050640000010200272004620050322800102080000201600002005020050111600211091010160000100010052321242441223312004315160000102004720047200512004720051
16002420046150116825800101080000108000050640000110200272004620046322800102080000201600002004620046111600211091010160000100010047311252021127262004315160000102005120047200512004720047
16002420046150115725800101080000108000050640000010200272004620046322800102080000201600002004620046111600211091010160000100010047311242021123322004315160000102004720051200472004720051

Test 5: throughput

Count: 16

Code:

  suqadd v0.8b, v16.8b
  suqadd v1.8b, v16.8b
  suqadd v2.8b, v16.8b
  suqadd v3.8b, v16.8b
  suqadd v4.8b, v16.8b
  suqadd v5.8b, v16.8b
  suqadd v6.8b, v16.8b
  suqadd v7.8b, v16.8b
  suqadd v8.8b, v16.8b
  suqadd v9.8b, v16.8b
  suqadd v10.8b, v16.8b
  suqadd v11.8b, v16.8b
  suqadd v12.8b, v16.8b
  suqadd v13.8b, v16.8b
  suqadd v14.8b, v16.8b
  suqadd v15.8b, v16.8b
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400593000695251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
160204400393000302516010810016000810016002050012801320400204003940039199771120018160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
160204400393003030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
160204400393000302516010810016000810016002050012801320400204003940039199776199901601202001600322003200644003940039111602011009910010016000010003601111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000301111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801700400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039300030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001111011801600400361600001004004040040400404004040040
16020440039300030251601841001600161001600285001280196040029400484004919976919986160128200160038200320076400484004811160201100991001001600001000002221012812311400451600001004004940049400494005040050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003930005225160010101600001016000050128000011400204003940039199967200191603272016000020320000400394003911160021109101016000010001002231181621117940036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001140020400394003919996320019160010201600002032000040039400391116002110910101600001000100223231916212161940036155160000104004040040400404004040040
16002440039300071125160010101600001016000050128000011400204003940039199963200191600102016000020320000400394003911160021109101016000010001002231191621171940036155160000104004040040400404004040040
1600244003929904625160010101600001016000050128000011400204003940039199963200191600102016000020320000400394003911160021109101016000010001002231191621119940036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001140020400394003919996320019160010201600002032000040039400391116002110910101600001000100243112016211191940036155160000104004040040400404004040040
160024400393000462516001010160000101600005012800001140020400394003919996320019160010201600002032000040039400391116002110910101600001000100223211916211191940036155160000104004040040400404004040040
160024400393000522516001010160000101600005012800000140020400394003919996320019160010201600002032000040039400391116002110910101600001000100223221916421919400363010160000104004040040400404004040040
1600244003930004625160010101600001016000050128000011400204003940039199963200191600102016000020320000400394003911160021109101016000010001002261191621191940036155160000104004040040400404004040040
160024400392990331251600101016000010160000501280000114002040039400392001132001916001020160000203200004003940039111600211091010160000100010022311191621119940036155160000104004040040400404004040040
160024400392999462516001010160000101600005012800001140020400394003919996320019160010201600002032000040039400391116002110910101600001000100243211916422197400363010160000104004040040400404004040040