Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUQADD (vector, 8H)

Test 1: uops

Code:

  suqadd v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723106125482510001000100039831303018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000373216112630100030383038303830383038
10043037230156125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030863038303830383038
10043037221014525482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230276125482510001000100039831313018303730372415328951000100020003037303711100110000075116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722008225482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  suqadd v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722539612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000307101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300861110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100001207101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000047101161129634100001003003830038300383003830038
102043003722502512954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225044129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100009007101161129634100001003003830038300383003830038
102043003722505362954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000612954825100101010000101000050427731303001830037300372828732889510010201000020200003003730037111002110910101000010000306402163229630010000103003830038300383003830038
10024300372250180612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250270612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010020006402162229630010000103003830038300383003830038
10024300372240420612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722503006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100000126402166229630010000103003830038300383003830038
100243003722502706129548251001010100081010000504277313130018300373003728287212876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250420612954825100101010000101000050427731313005430037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250240612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730085111002110910101000010000006402162229630210000103003830038300383003830038
10024300372250360612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730226111002110910101000010000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  suqadd v0.8h, v0.8h
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954725101001001000010010000500427716030018300373003728271728740101002001000820020016300373003711102011009910010010000100007811171716296450100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716030018300373003728271628741101002001000820020016300373003711102011009910010010000100007811171716296450100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716030018300373003728271728740101002001000820020016300373003711102011009910010010000100008411171816296460100001003003830038300383003830038
10204300372250061295472510100100100001001000050042825683001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171716296450100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716030018300373003728271728741101002001000820020016300373003711102011009910010010000100008111171716296450100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716030018300373003728271628741101002001000820020016300373003711102011009910010010000100004211171816296460100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716030018300373003728271728740101002001000820020016300373003711102011009910010010000100008411171816296460100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716030018300373003728271728741101002001000820020016300373003711102011009910010010000100007811171816296450100001003003830038300383003830038
102043003722400631295472510100100100001001000050042771603001830037300372827172874110100200100082002001630037300371110201100991001001000010000311171732296450100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771603001830037300372827162874010100200100082002001630037300371110201100991001001000010000611171716296460100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100105706402162229629010000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100001806402162229629010000103003830038300383003830038
100243003722506129547251001010100001010000504277160030018300373003728286032876710010201000020200003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722506129547251001010100001010000504277160030018300373003728286032876710010201000020200003003730037111002110910101000010010326402162229629010000103003830038300383003830038
100243003722540561295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100002106402162229629010000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100009606402162229629010000103003830038300383003830038
1002430037225061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000102002106402162229629010000103003830038300383003830038
10024300372250612954725100101010000101000050428121603001830037300372828603287671001020100002020000300373003711100211091010100001000010206402162229629010000103003830038300383003830038
1002430037224061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100003006402162229629010000103003830038300383003830038
1002430037224061295472510010101000010100005042771600300183003730037282860328767100102010000202000030037300371110021109101010000100009606402162229629010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd v0.8h, v8.8h
  movi v1.16b, 0
  suqadd v1.8h, v8.8h
  movi v2.16b, 0
  suqadd v2.8h, v8.8h
  movi v3.16b, 0
  suqadd v3.8h, v8.8h
  movi v4.16b, 0
  suqadd v4.8h, v8.8h
  movi v5.16b, 0
  suqadd v5.8h, v8.8h
  movi v6.16b, 0
  suqadd v6.8h, v8.8h
  movi v7.16b, 0
  suqadd v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651510000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651600000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
1602042006515000000029128801161008012410080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000010001111011901600200621600001002006620066200662006620066
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651510000002925801161008001610080028500640916120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066
160204200651500000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000010001111011901600200621600001002006620066200662006620066
160204200651510000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000000001111011901600200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200671500045258001010800001080000506400001152002720046200463228001020800002016000020046200461116002110910101600001000010030811820211972004315160000102005120051200512005120051
1600242004615000452580010108000010800005064000011520027200502004632280010208000020160000200462004611160021109101016000010000100308419202111092004315160000102004720047200472005120047
1600242004615000662580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010100100348411020211992004315160000102004720047200472004720047
160024200461500045258001010800001080000506400001152002720046200463528001020800002016000020046200461116002110910101600001000010029841820211892004315160000102004720047200472004720051
160024200461500023525800101080000108000050640000115200272004620046322800102080000201602102004620046111600211091010160000100001003384110202211082004315160000102004720047200472004720047
16002420050150005125800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000105100100308418202118102004315160000102004720047200472004720047
16002420046150004525800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100001003284110202119112004315160000102004720047200472004720047
160024200461500045258001010800001080000506400001152003120050200463228001020800002016000020046200461116002110910101600001000010034841920211992004315160000102004720047200472004720047
1600242004615000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010000100328411020211982004315160000102004720047200472004720047
16002420046150004525800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100001003285110202111082004315160000102004720047200472004720047

Test 5: throughput

Count: 16

Code:

  suqadd v0.8h, v16.8h
  suqadd v1.8h, v16.8h
  suqadd v2.8h, v16.8h
  suqadd v3.8h, v16.8h
  suqadd v4.8h, v16.8h
  suqadd v5.8h, v16.8h
  suqadd v6.8h, v16.8h
  suqadd v7.8h, v16.8h
  suqadd v8.8h, v16.8h
  suqadd v9.8h, v16.8h
  suqadd v10.8h, v16.8h
  suqadd v11.8h, v16.8h
  suqadd v12.8h, v16.8h
  suqadd v13.8h, v16.8h
  suqadd v14.8h, v16.8h
  suqadd v15.8h, v16.8h
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)d9ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400593000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101188160784003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132140020400394003919977761999016012020016003220032006440039400391116020110099100100160000100000111101189160884003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132040020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101187160784003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132040020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101188160834003601600001004004040040400404004040040
160204400392990000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101188160384003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132040020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101188160354003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101183160474003601600001004009140040400404004040040
160204401403001000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101189160734003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132040061402004003919977061999016012020016003220032006440039400391116020110099100100160000100000111101187160874003601600001004004040040400404004040040
160204400393000000030251601081001600081001600205001280132140020400394003919977061999016012020016003220032006440039400391116020110099100100160000100000111101188160784003601600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400502990000012004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002281161621189400360206160000104004040250400404004040040
16002440039300000000006125160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001040320001002283171641299400360206160000104004040040401004010240040
16002440039299010000008825160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002285161621164400360206160000104004040040400404004040040
1600244003930000000120046251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000103010047265191621285400360206160000104004040040400404004040040
16002440039299000000004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002285191621166400360206160000104004040040400404004040040
16002440039300000000004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002285191621147400360206160000104004040246400404004040040
160024400393000000024004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002285181621186400360206160000104004040040400404004040040
16002440039300000000004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002286181621189400360206160000104004040040400404004040040
16002440039299000000004625160010101600001016000050128000001540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002285181641165400360406160000104004040040400404004040040
160024400393000000000071125160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002285261621185400360206160000104004040040400404004040040