Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

SXTL (8H)

Test 1: uops

Code:

  sxtl v0.8h, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)031e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a6a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000373116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715061168625100010001000264521020182037203715713189510001000100020372037211001100002073116111786100020382038203820382038
100420371515061168625100010001000264521020182037203715713189510001000100020372037111001100000095116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  sxtl v0.8h, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)03080b18191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)72scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204200371500000000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000003071011611197910100001002003820038200382003820038
102042003715000000006119686251010010010000100100005002847521120018200372003718421031874510100200100002001000020037200371110201100991001001000010000006009071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752112001820037200371842103187451010020010000200100002003720037111020110099100100100001000000000071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000103071011611197910100001002003820038200382003820038
10204200371490000000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000200071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000206071011611197910100001002003820038200382003820038
1020420037150000000020381964183101481101001212310304660284752112001820037200841842108187451010020010000206103302013220037211020110099100100100001000000003071011611197910100001002003820038200382003820038
102042003715000000006119686251010010010000100100005002847521120018200372003718421031874510100200100002001000020037200371110201100991001001000010000003000779132131989415100001002013420181201812013220182
102042018315100110008919641125102091311004810010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000300071011611197910100001002003820038200382003820038
10204200371500000000611968625101001001000010010000500284752102001820037200371842103187451010020010000200100002003720037111020110099100100100001000000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)030b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024200371500000010119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000306403162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002520037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
100242003715000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010002015306402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001110000502847521020018200372003718443318767101632010000201000020037200371110021109101010000100000306402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100060006402162219786010000102003820038200382003820038
1002420037149000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006403162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
1002420037150000006119686251001010100001410000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100000306402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  sxtl v0.8h, v8.8b
  sxtl v1.8h, v8.8b
  sxtl v2.8h, v8.8b
  sxtl v3.8h, v8.8b
  sxtl v4.8h, v8.8b
  sxtl v5.8h, v8.8b
  sxtl v6.8h, v8.8b
  sxtl v7.8h, v8.8b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03070a191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80204200571501100050258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100100111511811611200350800001002003920039200392003920039
80204200381501100029258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039
8020420038150110001382580108100800081008002050064013220019020038200389977699898012020080032200800322003820038118020110099100100800001003230111511811611200350800001002003920039200392003920039
80204200381501100029258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039
80204200381501100050258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039
80204200381501100029258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039
80204200381501100029258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039
80204200381501100073258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039
80204200381501100029258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811622200350800001002003920039200392003920039
80204200381501100091258010810080008100800205006401322001902003820038997769989801202008003220080032200382003811802011009910010080000100000111511811611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242003915003682580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
800242003815002662580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020316332003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316332003580000102003920039200882003920039
800242003815001942580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020216332003580000102003920039200392003920039
800242003815001692580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316322003580000102003920039200392003920039
80024200381500392580010108000010803915064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316332003580000102003920039200392003920039
800242003814901442580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020216232003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100005020316232003580000102003920039200392003920039